Synthesis and Realization of N-bit Reversible Register File Used in Bus Organization of Processor Architecture

Majumder, Alak; Singh, Prasoon Lata; Chowdhury, Barnali; Rai, R.

doi:10.1016/j.procs.2015.07.491

“…Evaluation results of the proposed register file can be easily realised based on the results of Table 6. The proposed reversible design is compared to the existing related work (Majumder et al, 2015b) in terms of the number of garbage outputs and quantum cost. Comparison results demonstrate that the proposed design is more efficient than the existing work.…”

Section: Evaluation Of the Proposed Reversible Circuitsmentioning

confidence: 99%

Towards designing quantum reversible 32-bit MIPS register file

Gharajeh

¹

,

Haghparast

²

2020

IJHPSA

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Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

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“…Since decoder and multiplexer are applied in the register file, we also propose two reversible designs for these circuits. Main motivation of the paper is to decrease number of constant inputs, number of garbage outputs, and quantum cost compared to the existing reversible register file (Majumder et al, 2015b).…”

Section: Introductionmentioning

confidence: 99%

Towards designing quantum reversible 32-bit MIPS register file

Gharajeh

¹

,

Haghparast

²

2020

IJHPSA

0

View full text Add to dashboard Cite

Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

show abstract