Synthesis for Width Minimization in the Single-Electron Transistor Array

Liu, Chian-Wei; Chiang, Chang-En; Huang, Ching-Yi; Chen, Yung-Chih; Wang, Chun-Yao; Datta, Suman; Narayanan, Vijaykrishnan

doi:10.1109/tvlsi.2014.2386331

Cited by 6 publications

(1 citation statement)

References 27 publications

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“…Consequently, an algorithm that can minimize the number of product terms is demanded for the reconfigurable SET array synthesis flow. Recently, a synthesis flow has been proposed, featuring both product term minimization and architecture relaxation, for width minimization in reconfigurable SET array synthesis [16]. Basically, it utilizes the threshold network to reduce the number of product terms.…”

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confidence: 99%

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays

Chen

Huang

2015

VLSI Design, Automation and Test(VLSI-Dat)

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The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable singleelectron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.

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confidence: 99%