Synthesis of Balanced Ternary Reversible Logic Circuit

Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

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“…4b. According to the proofs stated in [47,48] ternary Feynman gate evaluation matrix can be expressed as:…”

Section: Ternary Controlled Feynman Gatementioning

confidence: 99%

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Monfared

Ciriani

Kettunen

et al. 2022

Quantum Inf Process

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“…Ternary logic can be divided into two types: balanced, which is expressed as (-1, 0, +1), and unbalanced. This latter unabalanced type comes in two forms, positive ternary (0, 1, 2) and negative ternary (-2, -1, 0) [26]. In this work, we focus on unbalanced positive ternary logic, where (0, 1, 2) = (GND, V DD /2, V DD ).…”

Section: Ternary Logic Gate Designmentioning

confidence: 99%

High-Density Memristor-CMOS Ternary Logic Family

Wang

Zhou

Eshraghian

et al. 2021

IEEE Trans. Circuits Syst. I

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This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

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“…This is called ternary numeral system which is mostly used. Another Balanced-Ternary representation having 1, 0, -1 as the logic levels is used after numeral system [14]. Ternary logic gates are the basic building blocks of any ternary circuits which switch among above three levels [7].…”

Section: Ternary Logic Gatesmentioning

confidence: 99%

Analysis of ternary multiplier using booth encoding technique

Kaur

Singh

Joshi

2015

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)

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This paper introduces a new approach to multiplication of ternary numbers. The whole multiplication is based on the efficient Booth Encoding technique that multiplies both positive as well as negative ternary numbers. Verilog HDL has been used to implement the ternary multipliers of 3bit, 8bit and 12bit. The HDL design is based on the Finite State Machine (FSM) and multiplexing techniques. The design is simulated using ModelSim SE 6.5 and synthesized using Xilinx ISE Design Suite 14.1. The results obtained from the proposed design in terms of delay, power and area have been compared with the conventional multiplier design.

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Synthesis of Balanced Ternary Reversible Logic Circuit

Cited by 14 publications

References 13 publications

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

High-Density Memristor-CMOS Ternary Logic Family

Analysis of ternary multiplier using booth encoding technique

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