Synthesis of delay-verifiable combinational circuits

Exact grading of multiple path delay faults

“…If any one of the three SPDF is singly sensitized, then the multiple path is not needed to be tested [3]. Such MPDFs which need not be tested are termed as redundant PDFs, and should be eliminated from the set of PDFs tested which will result in the set of nr-PDFs.…”

“…Existing enumerative and non-enumerative [1], [2], [8] fault grading techniques only examine the single path delay faults (SPDF).It has been shown that multiple path delay faults can affect the timing performance of a circuit [3]. Even though there exist methods for generating test patterns for this category of delay faults, there is no existing technique to calculate the exact coverage for the test sets aimed at multiple paths.…”

“…Section 5 presents a more evolving ZBDD based methodology for calculating only those PDFs that are useful in delay fault testing, which we term as non-redundant multiple path delay fault (nr-PDF). nr-PDFs are basically the set of primitive PDFs [3] identified by a given test set. The proposed method to identify the nr-PDF behaves linear to the number of MPDFs identified by the test set, in terms of basic ZBDD operations.…”

Generation of hazard identification functions

“…However, in the case where combinational logic generates signals that control internal variables of sequential circuits, the existence of hazards may lead to significant circuit malfunction. Moreover, combinational hazards must be considered in timing analysis and verification [9], [17], as well as test generation [4], [12]. In particular, in the context of testing, hazard identification becomes crucial in generating tests that will not be invalidated when applied to the circuit under test.…”

On primitive fault test generation in non-scan sequential circuits

“…Thus, an important problem in delay testing is to identify all faults that must be tested to guarantee that the tested circuit will function correctly at the tested speed and any lower speed. It has been shown that, for any combinational circuit, there exists a set of faults called primitive faults, that must be tested to guarantee correct timing [9,10]. The set of primitive faults may contain single and multiple path delay faults.…”