Synthesis of discrete controllers based on the signal Environment

Marchand, Hervé; Bournai, P.; Borgne, Michel Le; Guernic, Paul Le

doi:10.1007/978-1-4615-4493-7_54

Cited by 60 publications

(119 citation statements)

References 2 publications

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“…The advantage of our approach is validation or simulation results are compatible and reusable from one technique to another. For example, the schedulers generated from one technique (affine-clock systems) can be directly used for VCD simulation and Sigali-based modelchecking or controller synthesis [43,36], without semantics domain change. However, only brief results have been presented for the formal techniques as how to use these techniques are not in the scope of this paper.…”

Section: Discussionmentioning

confidence: 99%

“…We use the Sigali tool [43] as the model checker. Sigali relies on an implementation of polynomials by Ternary Decision Diagram (TDD) (for three valued logic) in the same spirit of Binary Decision Diagram (BDD) [44].…”

Section: Techniques For Formal Analysis and Simulationmentioning

confidence: 99%

“…After that, the executable code is generated for simulation. Associated tools, such as Sigali [43] and SynDEx [19], can be used for further verification and validation. In addition to ASME2SSME, there is another model transformation chain from functional models in Simulink to Signal.…”

Section: A Complete Tool Chainmentioning

confidence: 99%

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Polychronous modeling, analysis, verification and simulation for timed software architectures

Yu¹,

Ma²,

Gautier³

et al. 2013

Journal of Systems Architecture

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High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded systems architectural modeling in AADL and functional modeling in Simulink; an original clock-based timing analysis and validation of the overall system is achieved via a formal polychronous/multi-clock model of computation. In order to avoid semantics ambiguities of AADL and Simulink, their features related to real-time and logical time properties are first studied. We then endue them with a semantics in the polychronous model of computation. We use this model of computation to jointly analyze the non-functional real-time and logical-time properties of the system (by means of logical and affine clock relations). Our approach demonstrates, through several case-studies conducted with Airbus and C-S Toulouse in the European projects CESAR and OPEES, how to cope with the system-level timing verification and validation of high-level AADL and Simulink components in the framework of Polychrony, a synchronous modeling framework dedicated to the design of safety-critical embedded systems.

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Section: Discussionmentioning

confidence: 99%

Section: Techniques For Formal Analysis and Simulationmentioning

confidence: 99%

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Polychronous modeling, analysis, verification and simulation for timed software architectures

Yu¹,

Ma²,

Gautier³

et al. 2013

Journal of Systems Architecture

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show abstract

“…The Controller synthesis of symbolic finite state systems has been considered e.g. by Balemi et al (1993); Marchand et al (2000); Miremadi et al (2008a). The idea, as developed by Kumar et al (1993), was to encode subsets of the state-space by predicates and all the operations on state sets by predicate transformers, thus avoiding the enumeration of the state space while computing the supervisors 2 .…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we extend Kalyon et al (2009) in two ways: we consider masks that are coverings of the state space instead of partitions, and we improve the permissiveness of the control algorithm. In order to deal with the infiniteness of state space, the algorithms presented in this paper are symbolic: they do not enumerate individual states, but deal with the system variables by means of symbolic computations and the use of predicate transformers as done by Balemi et al (1993); Marchand et al (2000); Kumar et al (1993). Moreover, since the problem is undecidable as shown by Le Gall et al (2005), we keep using abstract interpretation techniques to get effective algorithms (i.e.…”

Section: Introductionmentioning

confidence: 99%

Symbolic Supervisory Control of Infinite Transition Systems Under Partial Observation Using Abstract Interpretation

Kalyon

Gall

Marchand

et al. 2011

Discrete Event Dyn Syst

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We propose algorithms for the synthesis of state-feedback controllers with partial observation of infinite state discrete event systems modelled by Symbolic Transition Systems. We provide models of safe memoryless controllers both for potentially deadlocking and deadlock free controlled systems. The termination of the algorithms solving these problems is ensured using abstract interpretation techniques which provide an overapproximation of the transitions to disable. We then extend our algorithms to controllers with memory and to online controllers. We also propose improvements in the synthesis of controllers in the finite case which, to our knowledge, provide more permissive solutions than what was previously proposed in the literature. Our tool SMACS gives an empirical validation of our methods by showing their feasibility, usability and efficiency.

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Using Controller-Synthesis Techniques to Build Property-Enforcing Layers

Altisen

Clodic

Maraninchi

et al. 2003

Programming Languages and Systems

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Abstract. In complex systems, like robot plants, applications are built on top of a set of components, or devices. Each of them has particular individual constraints, and there are also logical constraints on their interactions, related to e.g., mechanical characteristics or access to shared resources. Managing these constraints may be separated from the application, and performed by an intermediate layer.We show how to build such property-enforcing layers, in a mixed imperative/declarative style: 1) the constraints intrinsic to one component are modeled by an automaton; the product of these automata is a first approximation of the set of constraints that should be respected; 2) the constraints that involve several components are expressed as temporal logic properties of this product; 3) we use general controller synthesis techniques and tools in order to combine the set of communicating parallel automata with the global constraint.

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Synthesis of discrete controllers based on the signal Environment

Cited by 60 publications

References 2 publications

Polychronous modeling, analysis, verification and simulation for timed software architectures

Polychronous modeling, analysis, verification and simulation for timed software architectures

Symbolic Supervisory Control of Infinite Transition Systems Under Partial Observation Using Abstract Interpretation

Using Controller-Synthesis Techniques to Build Property-Enforcing Layers

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