Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

Verma, Amit; Verma, Ajay; Parandeh-Afshar, Hadi; Brisk, Philip; Ienne, Paolo

doi:10.1109/fpl.2010.15

Cited by 4 publications

(4 citation statements)

References 8 publications

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“…First, a hardware summation operator can take various forms: a multi-input adder (the operator handles a limited number of addends at once) [Tenca 2009;Verma et al 2010], an accumulator (operands are treated serially and their number can be very large) [Kulisch 2002;Luo and Martonosi 2000], a composite of the two operators [Morris and Prasanna 2005;Zhuo and Prasanna 2008], and other hardware approaches [Kapre and DeHon 2007;Tai et al 2012].…”

Section: Hardware Summationmentioning

confidence: 99%

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Ould-Bachir

David

2013

ACM Trans. Reconfigurable Technol. Syst.

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Advances in semiconductor technology brings to the market incredibly dense devices, capable of handling tens to hundreds floating-point operators on a single chip; so do the latest field programmable gate arrays (FPGAs). In order to alleviate the complexity of resorting to these devices in computationally intensive applications, this article proposes hardware schemes for the realization of addition-related floating-point operators based on the self-alignment technique (SAT). The article demonstrates that the schemes guarantee an accuracy as if summation was computed accurately in the precision of operator's internal mantissa, then faithfully rounded to working precision. To achieve such performance, the article adopts the redundant high radix carry-save (HRCS) format for the rapid addition of wide mantissas. Implementation results show that combining the SAT and the HRCS format allows the implementation of complex operators with reduced area and latency, more so when a fused-path approach is adopted. The article also proposes a new hardware operator for performing endomorphic HRCS additions and presents a new technique for speeding up the conversion from the redundant HRCS to a conventional binary format.

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Section: Hardware Summationmentioning

confidence: 99%

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Ould-Bachir

David

2013

ACM Trans. Reconfigurable Technol. Syst.

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“…Let e q be the quantization error defined as the difference between the data x and x Q . The data x can be modeled as the sum of the quantization process x Q and the quantization error e q (Verma, 2010).…”

Section: Floating-point and Fixed-point Codingmentioning

confidence: 99%

Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems

Blaiech

Khalifa

Boubaker

et al. 2014

International Journal of Embedded and Real-Time Communication Systems

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The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. The AAA-MWOG methodology will allow a considerable gain of circuit resources. This contribution is demonstrated by implementing the Learning Vector Quantization (LVQ) neural-networks model on the FPGA. The LVQ optimization is used to quantify vigilance states starting from processing the electroencephalographic signal. The precision-gain relation has been studied and reported.

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“…However, it has focused on the general synthesis of CS structures, not their selective use to accelerate floating-point operations. Other approaches use CS arithmetic internally to individual operations, but not between them [12,22].…”

Section: Related Workmentioning

confidence: 99%

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis

Liebig

Huthmann

Koch

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-Multiply-add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the applicationlevel speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and proposes two new architectures for floating-point fused multiply-adds, and also considers the impact of different in-fabric features of recent FPGA architectures. The units rely on different degrees of carry-save arithmetic improve performance by up to 2.5x over the closest state-of-the-art competitor.They are evaluated at the application level by modifying an existing high-level synthesis system to automatically insert the new units for computations on the critical path of three different convex solvers.

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Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

Cited by 4 publications

References 8 publications

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators

Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis

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