Synthesis of On-Chip Communication Architectures

Pasricha, Sudeep; Dutt, Nikil

doi:10.1016/b978-0-12-373892-9.00006-2

Cited by 40 publications

(27 citation statements)

References 95 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The NoC uses multiple processors, usually targeted for embedded applications and other applications [3,13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13].…”

Section: Introductionmentioning

confidence: 99%

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Khan

Ansari

2012

Open Computer Science

View full text Add to dashboard Cite

Abstract:The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3,13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 x 8 x 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.

show abstract

Section: Introductionmentioning

confidence: 99%

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Khan

Ansari

2012

Open Computer Science

View full text Add to dashboard Cite

show abstract

“…In NoC-based SoC design each of the functional modules should be designed to be latency-insensitive to support packet transactions which improve reliability and the speed of interconnection links, efficient link utilization is another advantage because only one part of the end-to-end path between functional modules is occupied by the traversing packets. For all these reasons, advanced bus architectures are gradually considering a packet transaction concept into their protocols [2,3]. NoC-based SoC design based on space wire interface standard of ESA (European Space Agency) supports packet transactions and known as SoCWire [4].…”

Section: Introductionmentioning

confidence: 99%

NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol

KumarTiwari¹,

Kumar²,

Sarin³

et al. 2012

IJCA

View full text Add to dashboard Cite

System on Chip Wire (SoCWire) is a Network on Chip (NoC) based design that composed of intellectual property blocks (IP) and interconnects based on space wire standard, was successfully implemented in Venus Express Monitoring Camera (VMC) mission and proposed to implement in Solar Orbital mission in future. The efficient and accurate implementation of SoCWire is the main concern in this work. A solution for single bit error detection and correction with hamming code for 8 bit data has been proposed, so that the accuracy of the design is improved with cost of extra resources and we can save nearly 19.2 μs time that is required to link re-initialization also the speed of the design is improved compared to conventional Codec. For routing data of many codec from one node to many other nodes SoCWire Switch is implement with crossbar based switch for 8 ports and achieved maximum frequency 179.743 MHz and 5% device utilization can be saved compared to [1]. These functionality and design performance are achieved with coding level change in VHDL for SoCWire. The design is synthesized on Xilinx ISE 12.1. The Target FPGA is XCVLX-60 which belongs to Xilinx Virtex 4 QPro.

show abstract

“…Due to this fact, in the last years, research on reducing the power consumed by the system has become of great interest. This can be done in several ways, but most of them are based on the issues that have been aforementioned: reduce the complexity of the system or some of its components, or decrease the number of elements without penalizing the system performance [88,92,99].…”

Section: Motivationmentioning

confidence: 99%

“…Otherwise, it has to store the packet while the medium is not free. This waiting time was the main cause of abandoning the paradigm of shared-medium networks, since it is proportional to the number of devices in the system, and in large systems this limitation strongly diminishes the time that each node can use the network, highly reducing the overall system performance [40,88,99]. This kind of networks is represented by several well-known commercial networks: Token Bus, Token Ring, and the first generations of Ethernet.…”

Section: Interconnection Network Basicsmentioning

confidence: 99%

“…This can be observed by comparing Figure 5.2(a) and Figure 5.4. This lower wiring density involves that RUFT can be more easily encapsulated in a cabinet, in off-chip systems; whereas in on-chip networks, this involves that RUFT would likely have less crosspoint in its layout, reducing in this way the number of metal layers used by the network which reduces the cost of the chip [88,99]. Additionally, the proposed topology helps in addressing some emerging constraints in system design due to the increasing density of nodes, such as power consumption, heat dissipation, packaging weight and size limitations.…”

Section: Advantages and Disadvantagesmentioning

confidence: 99%

See 1 more Smart Citation

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

Requena¹

View full text Add to dashboard Cite

Synthesis of On-Chip Communication Architectures

Cited by 40 publications

References 95 publications

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

NoC based Efficient RTL Design and Verification of SoCWire BUS Protocol

Low-Memory Techniques for Routing and Fault-Tolerance on the Fat-Tree Topology

Contact Info

Product

Resources

About