Synthesis of timed asynchronous circuits

Myers, Christopher; Meng, Tao

doi:10.1109/iccd.1992.276269

Cited by 31 publications

(29 citation statements)

References 5 publications

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“…Note that the ability to represent symbolic timing constraints between events is a powerful feature, and distinguishes ATDs as also the work of Amon et al [1], Fisler [12] and Clariso et al [9] from several earlier work [3,6,17,21,30]. The ability to represent assume and guarantee constraints of min, max and linear types in the same diagram makes it possible to perform more detailed analysis using ATDs than is possible with the representations used in [3,6,15,21].…”

Section: Abstract Timing Diagramsmentioning

confidence: 95%

“…ATDs are syntactically similar to commonly used waveform diagrams, timing diagrams [1,12], event-rule systems [3,21], event graphs [30], action diagrams [17], timing constraint graphs [6] and message sequence charts [15]. However, the analysis of interface timing constraints using ATDs differs from earlier approaches, as will be elaborated in Section 3.…”

Section: Abstract Timing Diagramsmentioning

confidence: 99%

“…The ability to represent assume and guarantee constraints of min, max and linear types in the same diagram makes it possible to perform more detailed analysis using ATDs than is possible with the representations used in [3,6,15,21]. In addition, the goal of our ATD-based analysis is to derive symbolic delay constraints for correct operation of interface circuits.…”

Section: Abstract Timing Diagramsmentioning

confidence: 99%

“…While representations similar to ATDs have been used earlier [1,3,6,12,17,21,30], applying these earlier approaches to our problem would require the designer to manually (or otherwise) identify all possible scenarios of interaction between sequencing and synchronization constraints, and then represent them explicitly in a combined diagram. This poses practical difficulties in a design-analyze-redesign setting, where a designer may wish to go through several iterations of modifying sequencing and synchronization constraints.…”

Section: Introductionmentioning

confidence: 99%

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Reasoning about synchronization in GALS systems

Chakraborty

Mekie

Sharma

2006

Form Method Syst Des

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Correct design of interface circuits is crucial for the development of System-onChips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.

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Section: Abstract Timing Diagramsmentioning

confidence: 95%

Section: Abstract Timing Diagramsmentioning

confidence: 99%

Section: Abstract Timing Diagramsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reasoning about synchronization in GALS systems

Chakraborty

Mekie

Sharma

2006

Form Method Syst Des

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“…While asynchronous logic circuit design adds additional area and performance overhead, as well as handshake circuit design complexity, asynchronous logic circuits can be synthesized automatically from state transition graphs [Meng87] [Meng89b] [Hung90]. Also, such circuits can be analyzed for testability [Beerel91] and timed asynchronous circuits, which are bounded by timing constraints, can be synthesized more efficiently [Myers93].…”

Section: Control Synchronizationmentioning

confidence: 99%

Synthesis of parallel hardware implementations from synchronous dataflow graph specifications

Williamson¹,

Lee²

Conference Record of the Thirtieth Asilomar Conference on Signals, Systems and Computers

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Automatic verification of timed circuits

Rokicki

Myers

1994

Computer Aided Verification

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This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on a behavioral semantics of timed trace theory. We present improvements to a geometric timing algorithm that take advantage of concurrency by using partial orders to reduce the time and space requirements of verification. This algorithm has been fully automated and incorporated into a design system for timed circuits, and experimental results demonstrate that this verification algorithm is practical for realistic examples.

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Synthesis of timed asynchronous circuits

Cited by 31 publications

References 5 publications

Reasoning about synchronization in GALS systems

Reasoning about synchronization in GALS systems

Synthesis of parallel hardware implementations from synchronous dataflow graph specifications

Automatic verification of timed circuits

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