Synthesizing a representative critical path for post-silicon delay prediction

Abstract

Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single critical path is too simplistic. This paper overcomes this problem by introducing the idea of synthesizing a representative critical path (RCP), which captures these complexities of the variations. We first prove that the requirement on the RCP is that it should be highly correlated with the circuit delay. Next, we present two novel algorithms to automatically build the RCP. Our experimental results demonstrate that over a number of samples of manufactured circuits, the delay of the RCP captures the worst case delay of the manufactured circuit. The average prediction error of all circuits is shown to be below 2.8% for both approaches. For both our approach and the critical path replica method, it is essential to guard-band the prediction to ensure pessimism: our approach requires a guard band 30% smaller than for the critical path replica method.

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

“…For smaller benchmarks (S1423 to S9234), we use a 3-level hierarchical model, resulting in This assumption is consistent with [6]. Consequently, for each region, we had two distinct random variables of L eff and V th .…”

“…If we assume the varying parameters in X have Normal distribution, then we haveds ∼ N (μs,σs) to also follow a Normal distribution [6]. The mean and standard deviation can be computed using the following equation as in [6]:…”

Process and Reliability Sensors for Nanoscale CMOS

“…The third step requires additional computation, which may not always be reasonably possible in the context of postsilicon adaptation. To bypass this step entirely, an alternative approach replaces the ensemble of ROs by a single synthesized test structure that replicates the delay characteristics of the original circuit 13 .…”

“…Since the RCP is an on-chip test structure, it can easily be used within existing post-silicon tuning schemes, e.g., by replacing the nominal critical path in a typical sense/respond adaptive loop 14 . Two heuristic approaches for building the RCP were presented in our work 13 , and were demonstrated to work effectively.…”

Enabling adaptability through elastic clocks

“…Figure 2) for proper e to match data path delays at all sign-off corners. The margins between the delay elements and the corresponding data path delays can be optimized using statistical methods [7].…”