Enabling adaptability through elastic clocks

Tuncer, E.; Cortadella, Jordi; Lavagno, Luciano

doi:10.1145/1629911.1629916

Cited by 10 publications

(4 citation statements)

References 10 publications

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“…Several prior proposals for GALS boundary crossings integrate pausible clocks with FIFO queues to synchronize data across an interface [6] [9] [10] [11] [12]. These designs typically require a fully asynchronous FIFO that services two-phase request and acknowledge signals to store data words in transit.…”

Section: Related Workmentioning

confidence: 99%

A Pausible Bisynchronous FIFO for GALS Systems

Keller

Fojtik

Khailany

2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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Many of the challenges of modern SoC design can be mitigated or eliminated with globally asynchronous, locally synchronous (GALS) design techniques. Partitioning a design into many synchronous islands introduces myriad asynchronous boundary crossings which typically incur high latency. We have designed a pausible bisynchronous FIFO that achieves low interface latency with a pausible clocking scheme. While traditional synchronizers have a non-zero probability of metastability and error, pausible clocking enables error-free operation by permitting infrequent slowdowns in the clock rate. Unlike prior pausible synchronizers, our circuit employs standard two-ported synchronous FIFOs, common circuit elements that integrate well with standard toolflows. The pausible bisynchronous FIFO achieves an average latency of 1.34 cycles across an asynchronous interface while using less energy and area than traditional synchronizers. TX Clock Valid Ready Valid Ready Data Out

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Section: Related Workmentioning

confidence: 99%

A Pausible Bisynchronous FIFO for GALS Systems

Keller

Fojtik

Khailany

2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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“…Elastic Clocks [13] emerge from the combination of the asynchronous pipelines by Muller [7] and Sutherland [12] and a methodology to automatically transform synchronous circuits into asynchronous. This methodology is known as Desynchronization [2].…”

Section: Elastic Clocksmentioning

confidence: 99%

Narrowing the margins with elastic clocks

Cortadella

Lavagno

Amiri³

et al. 2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.

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“…The principal idea is to replace clocked registers in synchronous designs with handshake registers. Elastix tool [19] implements this approach. The input of the tool is a finalised synchronous design.…”

Section: B Control Path Synthesismentioning

confidence: 99%

Secure Design Flow for Asynchronous Multi-valued Logic Circuits

Rafiev

Murphy

Yakovlev

2010

2010 40th IEEE International Symposium on Multiple-Valued Logic

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Abstract-The purpose of secure devices such as smartcards is to protect secret information against software and hardware attacks. Implementation of the appropriate protection techniques often implies non-standard methods that are not supported by the conventional design tools. In the recent decade the designers of secure devices have been working hard on customising the workflow. The presented research aims to collect the up-to-date experiences in this area and create a generic approach to the secure design flow that can be used as guidance by engineers.In the presented paper the emphasis is put on multi-valued logic synthesis and asynchronous system design. The proposed flow employs the tool based on higher radix and mixed radix Reed-Muller expansions [1], power-balanced logic component libraries and TiDE design environment [2]. The challenge of the research here is interfacing between different EDA tools and technologies. An example is also presented and described from the view of the system designer.

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Enabling adaptability through elastic clocks

Cited by 10 publications

References 10 publications

A Pausible Bisynchronous FIFO for GALS Systems

A Pausible Bisynchronous FIFO for GALS Systems

Narrowing the margins with elastic clocks

Secure Design Flow for Asynchronous Multi-valued Logic Circuits

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