A Pausible Bisynchronous FIFO for GALS Systems

Abstract

Many of the challenges of modern SoC design can be mitigated or eliminated with globally asynchronous, locally synchronous (GALS) design techniques. Partitioning a design into many synchronous islands introduces myriad asynchronous boundary crossings which typically incur high latency. We have designed a pausible bisynchronous FIFO that achieves low interface latency with a pausible clocking scheme. While traditional synchronizers have a non-zero probability of metastability and error, pausible clocking enables error-free operation by permitting infrequent slowdowns in the clock rate. Unlike prior pausible synchronizers, our circuit employs standard two-ported synchronous FIFOs, common circuit elements that integrate well with standard toolflows. The pausible bisynchronous FIFO achieves an average latency of 1.34 cycles across an asynchronous interface while using less energy and area than traditional synchronizers. TX Clock Valid Ready Valid Ready Data Out

A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules

“…[10] and [11] proposed an interface circuit based on FIFOs to transfer data between local synchronous modules in GALS systems. The interface circuits consist of FIFOs and FIFO controllers.…”

“…Compared with [2], [3], and [7]- [11] where the target is the interface circuit between synchronous modules, we focus on the interface circuit between synchronous and asynchronous modules. We are going to reduce the power consumption of a system by using asynchronous modules.…”

Measurements of metastability in MUTEX on an FPGA

“…When two or more parties communicate with each other asynchronously, synchronization mechanisms for them must be designed carefully since the metastability can be occurred. A simple "brute-force" synchronizer (two or more cascaded FFs) suppresses the probability of metastability to a negligible value [5]. Unfortunately, it introduces a high latency that degrades the performance of a system.…”

Modeling and Design for Low Power and Variation Tolerance in Integrated Circuits

“…For instance, in a network-on-chip (NOC) scenario, an extra 4-cycle latency per router of a 2-cycle baseline latency is well-tolerated across different benchmarks and causes an average performance loss of only 3.5%. As described previously and shown in Figure 3.19, with an estimated increase in latency by less than 4% with recent fast-crossing interface circuits such as [54] and the inherent latency-tolerance of GPUs, we safely expect the impact on GPU performance to be very low. To summarize the above section, we present models and quantitatively estimate the benefits of fine-grained GALS adaptive clocking scheme for HP processors compared to the traditional adaptive clocking scheme.…”

“…The signals crossing the boundaries of the various asynchronous clock domains are required to be synchronized to avoid operational failure. A simple implementation of a synchronizer called the brute-force synchronizer involves a series of flip-flops that samples a signal from one clock domain to FIFO) queues[54] for efficient transfer of data across the boundaries. A more fitting candidate for GALS schemes with adaptive clocks is potentially the pausible bisynchronous FIFO[54] that integrates well into standard tools.…”