System considerations for robust time and space partitioning in Integrated Modular Avionics

Littlefield-Lawwill, J.; Kinnan, L.

doi:10.1109/dasc.2008.4702751

Cited by 16 publications

(6 citation statements)

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“…It becomes much more complex when such systems deploy multi-core processors. In single-core systems temporal isolation with respect to shared resources has to be considered only if Direct Memory Access (DMA)-capable peripheral devices or interrupts are enabled [7]. By means of abstraction layers, device drivers and disabling of unpredictable interrupts it is possible to avoid any unintended parallel accesses of processing cores and peripheral devices to memory.…”

Section: Resource Capacity Enforcementmentioning

confidence: 99%

Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement

Nowotsch¹,

Paulitsch²,

Bühler

et al. 2014

2014 26th Euromicro Conference on Real-Time Systems

124

104

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Abstract-The performance and power efficiency of multi-core processors are attractive features for safety-critical applications, as in avionics. But increased integration and average-case performance optimizations pose challenges when deploying them for such domains. In this paper we propose a novel approach to compute a interference-sensitive Worst-Case Execution Time (isWCET) considering variable accesses delays due to the concurrent use of shared resources in multi-core processors. Thereby we tackle the problem of temporal partitioning as it is required by safety-critical applications. In particular, we introduce additional phases to state-of-the-art timing analysis techniques to analyse an applications resource usage and compute an interference delay. We further complement the offline analysis with a runtime monitoring concept to enforce resource usage guarantees. The concepts are evaluated on Freescale's P4080 multi-core processor in combination with SYSGO's commercial real-time operating system PikeOS and AbsInt's timing analysis framework aiT. We abstract real applications' behavior using a representative task set of the EEMBC Autobench benchmark suite. Our results show a reduction of up to 75% of the multi-core Worst-Case Execution Time (WCET), while implementing full transparency to the temporal and functional behavior of applications, enabling the seamless integration of legacy applications.

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Section: Resource Capacity Enforcementmentioning

confidence: 99%

Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement

Nowotsch¹,

Paulitsch²,

Bühler

et al. 2014

2014 26th Euromicro Conference on Real-Time Systems

124

104

View full text Add to dashboard Cite

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“…Such mechanisms raise new issues regarding several high-level requirements including robust partitioning. Existing studies, such as [7] and [8] have identified some of those mechanisms and their related issues for multicore certification.…”

Section: Multicore Specific Issues With Robust Partitioningmentioning

confidence: 99%

Ensuring robust partitioning in multicore platforms for IMA systems

Gatti

Jean

Pautet

et al. 2012

2012 IEEE/AIAA 31st Digital Avionics Systems Conference (DASC)

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“…For aircraft, only a limited number of LRUs can be added because they have space, weight, and power (SWaP) constraints. Therefore, to deal with more features in aircraft, the IMA architecture [17,18] has been proposed.…”

Section: Avionics Systemmentioning

confidence: 99%

“…However, many systems operate on one hardware backbone, and it is necessary to guarantee the execution of each system. For this, the partitioning mechanism [18] following the ARINC 653 standard [13] is applied to avionics systems. Furthermore, virtualization-based methods, such as a hypervisor, provide legacy software compatibility with integrated hardware [20,21].…”

Section: Avionics Systemmentioning

confidence: 99%

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

et al. 2020

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Multicore architecture is applied to contemporary avionics systems to deal with complex tasks. However, multicore architectures can cause interference by contention because the cores share hardware resources. This interference reduces the predictable execution time of safety-critical systems, such as avionics systems. To reduce this interference, methods of separating hardware resources or limiting capacity by core have been proposed. Existing studies have modified kernels to control hardware resources. Additionally, an execution model has been proposed that can reduce interference by adjusting the execution order of tasks without software modification. Avionics systems require several rigorous software verification procedures. Therefore, modifying existing software can be costly and time-consuming. In this work, we propose a method to apply execution models proposed in existing studies without modifying commercial real-time operating systems. We implemented the time-division multiple access (TDMA) and acquisition execution restitution (AER) execution models with pseudo-partition and message queuing on VxWorks 653. Moreover, we propose a multi-TDMA model considering the characteristics of the target hardware. For the interference analysis, we measured the L1 and L2 cache misses and the number of main memory requests. We demonstrated that the interference caused by memory sharing was reduced by at least 60% in the execution model. In particular, multi-TDMA doubled utilization compared to TDMA and also reduced the execution time by 20% compared to the AER model.

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System considerations for robust time and space partitioning in Integrated Modular Avionics

Cited by 16 publications

References 0 publications

Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement

Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement

Ensuring robust partitioning in multicore platforms for IMA systems

Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS

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