System design using Khan process networks: the Compaan/Laura approach

Stefanov, Todor; Zissulescu, Claudiu; Turjan, Alexandru; Kienhuis, Bart; Deprette, E.

doi:10.1109/date.2004.1268870

Cited by 93 publications

(114 citation statements)

References 15 publications

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“…These operations may be interleaved in any order, and a process may read or write an arbitrary number of tokens from or into a FIFO. Each FIFO implementation has bounded capacity [8]. A process blocks on a read or write when the FIFOs does not have enough input data or output space, respectively.…”

Section: Application Models Of Computationmentioning

confidence: 99%

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Nejad

Molnos

Goossens

2011

2011 14th Euromicro Conference on Digital System Design

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Abstract-Multi-processor Systems on Chip (MPSoCs) execute multiple applications concurrently. These applications may belong to different domains, i.e., may have firm-, soft-, or non-realtime requirements. A composable system simplifies system design, integration, and verification by avoiding the inter-application interference. Existing work demonstrates composability for applications expressed using a single model of computation. For example, Kahn Process Network (KPN) and dataflow are two common data-driven parallel models of computation, each with different properties and suited for different application domains. This paper extends existing work with support for concurrent, composable execution of KPN and dataflow applications on the same MPSoC platform. We formalize a unified execution model by defining its operations that implement the different models of computation on the MPSoC, and discuss the trade-offs involved. Our experiments indicate that multiple applications modeled in KPN and dataflow run composably on an MPSoC platform.

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Section: Application Models Of Computationmentioning

confidence: 99%

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Nejad

Molnos

Goossens

2011

2011 14th Euromicro Conference on Digital System Design

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“…This tool-set, consisting of the Compaan [34,37] and Laura [34,40] tools, is capable of transforming a sequential application specification into a parallel application specification (a KPN to be more specific), and subsequently allows for producing synthesizable very high-level design language (VHDL) code that implements the application specified by the KPN for a specific field programmable gate-array (FPGA) platform. Figure 5 illustrates how the Compaan and Laura tools can be applied for the purpose of model calibration.…”

Section: Calibration Of Dedicated Model Componentsmentioning

confidence: 99%

“…The Kahn application models, which are implemented in C++, are either derived by hand (e.g. from existing sequential code) or are generated by tools such as Compaan [34,37] -which will be discussed later on -or KPNgen [39].…”

Section: The Sesame Environmentmentioning

confidence: 99%

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel

Thompson

Polstra

et al. 2007

J Sign Process Syst Sign Image

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Abstract. High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such highlevel modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

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“…2.1) to generate RTL. In [22], the authors present a system design approach using a different model, called the Kahn process network model, which can be used to generate RTL code for applications written in MATLAB to be automatically mapped onto FPGA-and microprocessor-based platforms. In [14], the authors propose a heterogeneous system modeling approach based on dataflow graphs for synthesis on FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Model-based mapping of reconfigurable image registration on FPGA platforms

Sen

Hemaraj

Plishker

et al. 2008

J Real-Time Image Proc

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Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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System design using Khan process networks: the Compaan/Laura approach

Cited by 93 publications

References 15 publications

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Model-based mapping of reconfigurable image registration on FPGA platforms

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