System in wafer-level package technology with RDL-first process

Motohashi, Norikazu; Kimura, Takehiro; Mineo, Kazuyuki; Yamada, Yusuke; Nishiyama, Tomohiro; Shibuya, Koujiro; Kobayashi, Hiroaki; Kurita, Yasuo; Kawano, Motoharu

doi:10.1109/ectc.2011.5898492

Cited by 45 publications

(4 citation statements)

References 8 publications

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“…Refs. [19,20], one of the challenges of chip-first (either die faceup or face-down) FOWLP and the key reasons for them to introduce the chip-last or RDL-first FOWLP is the production yield during the RDL process is low because the KGDs are already embedded. This is true only if the chip-last (RDL-first) FTI is fully functionally tested before the chip-to-wafer bonding.…”

Section: Reasons For Chip-last or Rdl-first According Tomentioning

confidence: 99%

“…During IEEE/ESTC2010 and ECTC2011, NEC (now Renesas) presented a couple of papers on system in wafer-level package (SiWLP) [19], and "RDL-first" FOWLP [20]. These papers are based on their SMArt chip connection with feed through interposer packaging technology for interchip wide-band data transfer [21,22] and 3D stacked memory integrated on logic devices [23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

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Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Section: Reasons For Chip-last or Rdl-first According Tomentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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“…W ith the increasing cost of advanced wafer manufacturing processes in a foundry, the concept of chiplet has gained increasing attention in the post-Moore era [1][2]. Chiplet is the concept of breaking down the functions of a single system on chip into numerous small chips and then using advanced packaging technology (MCM/2.5D/3-D, etc.)…”

Section: Introductionmentioning

confidence: 99%

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

Chen,

Bian,

Liu

et al. 2024

Journal of Microelectronics and Electronic Packaging

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The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.

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“…If the die shift issues in die-first FOWLP are mitigated, the production yield would be further increased, leading to drastic cost reduction. The biggest advantage of the die-first FOWLP is that wire bonding, printable wiring, and solder bumping are not required for connecting the neighboring dies and there are no additional packaging processes due to the embedded structure [25] [26]. In our embodiment of this approach, the high flexibility is achieved by the unique structure of FlexTrate TM consisting of [27].…”

Section: Introductionmentioning

confidence: 99%

Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration

Fukushima

Alam

Hanna

et al. 2018

IEEE Trans. Compon., Packag. Manufact. Technol.

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A technological platform is established for scalable flexible hybrid electronics (FHE) based on a novel fan-out wafer level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate TM . These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm-sqaure Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this work, 8-µm-pitch die-to-die interconnections are successfully implemented over a stress buffer layer (SBL) formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate TM are characterized. Index Terms-flexible substrate, high-density interconnect, heterogeneous integration, Fan-Out Wafer-level Packaging (FOWLP), Polydimethylsiloxane (PDMS), and flexible hybrid electronics (FHE).

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System in wafer-level package technology with RDL-first process

Cited by 45 publications

References 8 publications

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)

Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration

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