System-level clock jitter modeling for DDR systems

Shim, Yujeong; Oh, Dan; Khor, Chuan Thim; Dhavale, Bipin; Chandra, Sunitha; Chow, Daniel; Ding, Weichi; Chand, Kundan; Aflaki, Aman; Sarmiento, Mayra

doi:10.1109/ectc.2013.6575749

Cited by 16 publications

(6 citation statements)

References 3 publications

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“…At the memory-system level, both DQ data and the corresponding clock will have PSIJ but it is the net impact on link timing margin that is critical. If, at the link receiver, a sinusoidal jitter on data and clock are of the same amplitude and phase, then the data jitter is considered "tracked" by the clock as there is no net effect on the system [6,7]. Jitter tracking can occur at very low jitter frequency and each time the difference in path delays of data and clock cause a rotation through 360° of relative phase.…”

Section: Tx Psij and Link Psijmentioning

confidence: 99%

Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface

Madden

Lan

Yan

et al. 2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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Section: Tx Psij and Link Psijmentioning

confidence: 99%

Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface

Madden

Lan

Yan

et al. 2013

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

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“…The examples of the PDN impedance profile modeling methodologies and extraction are shown in [17,18]. Current switching profiles can be simulated based on transient simulation or estimated at the early design stage [18].…”

Section: 𝐽(𝑓) = 𝑉(𝑓) × 𝑆(𝑓) (4)mentioning

confidence: 99%

“…Since a distorted sinusoidal waveform is typically induced at the PGSV, the jitter sensitivity function to supply noise frequency, 𝑆(𝑓), can be determined via transient simulation by sweeping the frequency of the voltage noise over the frequency range of interest at which the device is more sensitive to the jitter. Nevertheless, the derivation of The examples of the PDN impedance profile modeling methodologies and extraction are shown in [17,18]. Current switching profiles can be simulated based on transient simulation or estimated at the early design stage [18].…”

Section: 𝐽(𝑓) = 𝑉(𝑓) × 𝑆(𝑓) (4)mentioning

confidence: 99%

“…Nevertheless, the derivation of The examples of the PDN impedance profile modeling methodologies and extraction are shown in [17,18]. Current switching profiles can be simulated based on transient simulation or estimated at the early design stage [18]. The noise-to-jitter transfer function sensitivity is determined by characterizing the IO buffer under PGSV noise and measuring the output eye jitter.…”

Section: 𝐽(𝑓) = 𝑉(𝑓) × 𝑆(𝑓) (4)mentioning

confidence: 99%

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Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Souilem

Melício

Dghais

et al. 2022

Sensors

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This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

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“…Since data path is less sensitive to high frequency noise and PDN impedance is low at GHz range, the compensation path of JEqualizer increases high frequency switching noise and reduce low/mid frequency noise as inserting switching during non-transition of the main path. Based on accurate supply noise induce jitter simulation [6]- [8], JEqualizer reduces supply noise induced jitter by 80% without huge on-die/package decoupling capacitors and with only 1% of area over-head. Ultimately, this circuitry facilitates less cost, versatility and high jitter performance.…”

Section: Introductionmentioning

confidence: 99%

A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

Shim

Hoang

et al. 2014

2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)

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As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.

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System-level clock jitter modeling for DDR systems

Cited by 16 publications

References 3 publications

Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface

Power integrity of a 4.8Gbps-per-link low-swing single-ended-I/O server memory interface

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

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