System-level estimation of threshold voltage degradation due to NBTI with I/O measurements

Abstract

With the scaling of CMOS technology, Negative Bias Temperature Instability (NBTI) and Process Variations (PV) are serious issues for transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a method to determine the initial average channel length (L) and threshold voltage () for individual chips, together with NBTI model parameters through I/O measurements. We determine a relationship between , , and ground signal variation and fit models to the simulation results. The voltage of the ground signal is used for the calculation of the delay and amplitude shifts which are used to extract PV and NBTI parameters. Then, we calculate the lifetime for each chip individually using calibrated NBTI models, accounting for process variations. The methodology enables the extraction of NBTI and PV model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to differentiate chips that have different parameters initially and are more or less vulnerable to NBTI.

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system

“…Under gate bias and temperature stress with the Poisson distribution, the number of defects is a function of time. A detailed explanation is available in [4], [15]. The threshold voltage is proportional to the number of defects [14], and this produces the following statistics for the threshold voltage:…”

“…3and (4) can be correctly adjusted as a function of stress conditions and the scenario. The phi value depends on the supply voltage as well, not just the temperature and the test bench [15].…”

“…-ing point unit (FPU), and a finite impulse response (FIR) filter) and test benches have been considered as case studies. Detailed information for each circuit is in [15].…”

“…5(b) and (c). The detailed extraction method is explained in [15], [22]. The extracted delay and amplitude shift data under different test conditions at different time points is illustrated in Fig.…”

“…The trend in ∆Vth is modeled to extract A and B, which are then compared with the original values for A and B. More details are provided in [15]. TABLE I shows the average error rate for coefficients A and B, which are extracted by several simulation runs for different circuits and test  (A) (%) 5.48 4.91 5.12 4.30 3.90 3.49  (B) (%) 3.91 3.37 3.68 3.29 3.38 3.14 benches using full chip simulations.…”