System-level modeling of dynamically reconfigurable hardware with SystemC

Pelkonen, Antti; Masselos, K.; Cupak, M.

doi:10.1109/ipdps.2003.1213321

Cited by 37 publications

(16 citation statements)

References 4 publications

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“…Modelling of dynamic reconfigurable systems is done with SystemC in [13] which is one of the most referred works in this topic. The main contribution of that work is to collect all RMs of an RR into a module called Dynamically Reconfigurable Fabric (DRCF) and configure a module to the RR when it is requested from other parts of the design.…”

Section: High-level Modelling Of Run-time Reconfigurable Designsmentioning

confidence: 99%

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Uchevler

Svarstad

2018

International Journal of Reconfigurable Computing

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

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Section: High-level Modelling Of Run-time Reconfigurable Designsmentioning

confidence: 99%

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Uchevler

Svarstad

2018

International Journal of Reconfigurable Computing

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“…Another approach for simulating the performance of reconfigurable architectures based on SystemC has been presented in [1]. Similarly, in [7], a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC is presented. However, all these approaches are limited to design time exploration and only deal with the static nature of the architecture and/or the applications.…”

Section: Related Workmentioning

confidence: 99%

Evaluation of runtime task mapping heuristics with rSesame - a case study

Sigdel¹,

Thompson²,

Galuzzi³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.

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“…An exception to this is used in the ADRIATIC project [12]. In this approach, mutual exclusive modules are to be described as bus slaves.…”

Section: Related Workmentioning

confidence: 99%

OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems

Schallenberg

Nebel

Herrholz

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

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System-level modeling of dynamically reconfigurable hardware with SystemC

Cited by 37 publications

References 4 publications

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Evaluation of runtime task mapping heuristics with rSesame - a case study

OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems

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