System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

Conte, Thomas M.; Menezes, Kishore N.; Sathaye, Sumedh W.; Toburen, Mark C.

doi:10.1109/92.831433

Cited by 30 publications

(21 citation statements)

References 13 publications

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“…Marculescu [35] presents a profile-driven energy optimization strategy for superscalar architectures. Conte et al [14] also discuss adaptive execution for power efficiency. Our work is different from these in at least two important aspects.…”

Section: On-chip Multiprocessor and Loop Parallelizationmentioning

confidence: 99%

Optimizing array-intensive applications for on-chip multiprocessors

Kadayif

Kandemir

Chen

et al. 2005

IEEE Trans. Parallel Distrib. Syst.

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Abstract-With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a set of code optimization strategies. We first evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using a different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67 percent energy savings at the expense of up to 17 percent performance loss in a set of array-intensive applications. To eliminate this performance penalty, we also discuss and evaluate a processor preactivation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut down and preactivation can be very effective in reducing energy consumption without increasing execution time. We then generalize our strategy and present an application parallelization strategy based on integer linear programming (ILP). Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each loop nest based on the objective function and additional compilation constraints provided by the user/programmer. Our initial experience with this constraint-based optimization strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under multiple energy and performance constraints.

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Section: On-chip Multiprocessor and Loop Parallelizationmentioning

confidence: 99%

Optimizing array-intensive applications for on-chip multiprocessors

Kadayif

Kandemir

Chen

et al. 2005

IEEE Trans. Parallel Distrib. Syst.

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“…al. [6] separated architectural and technology components of dynamic power, and used a near-optimal search to tailor a processor design to different benchmarks. While Conte's model used the trace-driven simulation to collect high level statistics about pipeline stages, our model dwells into greater details of each processor component.…”

Section: Related Workmentioning

confidence: 99%

Co-optimization of Performance and Power in a Superscalar Processor Design

Zhu

Wong

Andrei

2006

Emerging Directions in Embedded and Ubiquitous Computing

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Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. The co-optimization requires exploration into a huge design space containing both performance and power factors, whose size is over costly for extensive traditional simulations. This paper describes a unified model covering both performance and power. The model consists of workload parameters, architectural parameters plus corresponding power parameters with a good degree of accuracy compared with physical processors and simulators. We apply the model to the problem of co-optimizing the power and performance. Concrete insights into the tradeoffs of designs for performance and power are obtained in the process of co-optimization.

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“…The work in [11] proposes a system-level technique to find low-power high performance superscalar processors tailored to specific user applications. Low-power design optimization techniques for high performance processors have been investigated in [14] from the architectural and compiler standpoints.…”

Section: Introductionmentioning

confidence: 99%

“…A coarse-grained static high-level code metrics is code compactness, while more accurate metrics are based on code profiling. Other system-level estimation and exploration methods have been recently proposed in literature targeting power-performance tradeoffs from the system-level standpoint [11], [12], [13], [14], [15], [16].…”

Section: Introductionmentioning

confidence: 99%

Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems

Agosta

Palermo

Silvano

2004

Proceedings of the 2004 ACM Symposium on Applied Computing

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The exploration of the architectural design space in terms of energy and performance is of mainly importance for a broad range of embedded platforms based on the SystemOn-Chip approach. This paper proposes a methodology for the co-exploration of the design space composed of architectural parameters and source program transformations. A heuristic technique based on Pareto Simulated Annealing (PSA) has been used to efficiently span the multi-objective co-design space composed of the product of the parameters related to the selected program transformations and the configurable architecture. The analysis of the proposed framework has been carried out for a parameterized superscalar architecture executing a selected set of benchmarks. The reported results show the effectiveness of the proposed co-exploration with respect to the independent exploration of the transformation and architectural spaces to efficiently derive approximate Pareto curves.

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System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

Cited by 30 publications

References 13 publications

Optimizing array-intensive applications for on-chip multiprocessors

Optimizing array-intensive applications for on-chip multiprocessors

Co-optimization of Performance and Power in a Superscalar Processor Design

Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems

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