System-level requirements for implementing wide dynamic range pulse-modulated polar transmitters

Abstract

This paper presents an architecture for implementing a wide dynamic range pulse-modulated polar transmitter and its system-level requirements. For validation of the proposed architecture, a simulation platform is constructed using a CDMA2000 1X signal. The system level simulation results show that the architecture can achieve over 80-dB dynamic range easily and accurately while passing the spectral requirements of the CDMA2000 standard. Using the simulation results, design specifications of various blocks required for implementing the proposed architecture are derived and reported. Compared to a conventional linear transmitter architecture that uses two high-resolution digital-to-analog converters (DACs), the proposed architecture requires only two low-resolution DACs and an all-digital pulse width modulation block. The eased DAC requirements would significantly reduce the cost and space for implementing a radio-frequency transmitter.

CMOS polar transmitter with wide power control range

“…As demonstrated through the simulation in [7], a high‐efficiency linear power amplification achieving 80 dB of PCR is possible by using off‐the‐shelf components to implement the pulse‐modulated polar transmitter (PMPT) architecture. To achieve a dynamic power control, the supply voltage is first altered to control the output power for high power levels.…”