System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

Santos, Carla Eliete Iochims dos; Vivet, Pascal; Dutoit, Denis; Garrault, Philippe; Peltier, Nicolas; Reis, Ricardo

doi:10.1109/3dic.2013.6702379

Cited by 11 publications

(2 citation statements)

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“…Finally, the obtained values have been scaled based on the relative area occupied by the TSVs in each individual layer in the 3-D stack. This approximation method has been adopted from [56], and it has been necessary since 3D-ICE does not support modeling TSVs. More accurate models and analysis of the analysis of the effect of copperfilled TSVs on heat transfer has been performed in [57].…”

Section: B Thermal Analysismentioning

confidence: 99%

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish

Rossi

Loi

et al. 2015

IEEE Trans. VLSI Syst.

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Large required size, and tolerance to latency and variations in memory access time make L2 memory a suitable option for 3-D integration. In this paper, we present a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its network-on-chip interfaces offering high-bandwidth memory access with low average latency. Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows stacking of multiple identical memory dies (MDs), supports multiple outstanding transactions, and achieves high clock frequencies due to its highly pipelined nature. We implemented our design with STMicroelectronics CMOS-28-nm low-power technology and obtained a clock frequency of 500 MHz (limited by the access time of the memory arrays, whereas its logic components can operate up to 1 GHz), up to eight stacked dies (4 MB) with a memory density loss of 9%. Benchmark simulation results demonstrate that the addition of 3-D-NUMA to a multicluster system can lead to an average performance boost of 34%. Furthermore, experiments and estimations confirm that 3-D-NUMA is energy and power efficient (38% power reduction due to an architectural clock gating scheme), temperature friendly (over 40°C temperature reduction), and has unique features suitable for low-cost manufacturing (2.3× cost reduction due to identical MD layouts). Finally, 22% yield improvement is achievable in 3-D-NUMA compared with its 2-D counterparts, using the state of the art through-silicon-via technologies.Index Terms-3-D integration, nonuniform memory access (NUMA), physical implementation, tightly coupled data memory.

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Section: B Thermal Analysismentioning

confidence: 99%

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish

Rossi

Loi

et al. 2015

IEEE Trans. VLSI Syst.

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“…Measured temperature data are used for comparisons with simulation results for steady-state and transient analyses considering multiple power scenarios, corresponding each to a specific set of active heaters (more details in [6]). Fig.…”

Section: Silicon Correlationmentioning

confidence: 99%

Thermal modeling methodology for efficient system-level thermal analysis

Santos

Vivet

Matter³

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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Heat dissipation is assumed to be one of the major challenges in the promising 3D integration technology. Very fine grain structures like TSVs and µ-bumps have considerable impact on heat dissipation properties. However, properly considering individual details of multi-length scale systems is still a challenge for efficient system-level thermal analysis. This paper presents a compact thermal modeling approach targeting fast steady-state and transient thermal analysis. The proposed method associates material homogenization and formal reduction techniques for model simplification, enabling to concurrently handle fine grain structures and constraints from board and package modeling. As a result, a dynamic compact thermal model is achieved offering system-level exploration capabilities. Simulation results of a complete system including a packaged 65nm memory-on-logic 3D circuit, socket and board show the thermal model is able to capture hotspot effects with fast simulation times. Comparisons with temperature measurements on the fabricated circuit demonstrate that accurate system-level thermal model of multi-length scale systems is feasible, showing an average error of 3.96% for steady-state temperature. Secondly, this paper reports an investigation study to show the thermal impact of TSV arrays, vertical stacking and die thickness, showing that 3D integration technology parameters considerably impacts silicon temperature and therefore should be properly modeled for accurate thermal analysis.

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