System-on-a-Chip (SoC) Based Hardware Acceleration  for Video Codec

Niu, Xinwei; Fan, Jeffrey

doi:10.4236/opj.2013.32b028

Cited by 3 publications

(1 citation statement)

References 17 publications

(19 reference statements)

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“…Saat ada objek terdeteksi, citra yang akan disimpan adalah citra masukan, sedangkan saat tidak ada objek yang terdeteksi maka citra yang disimpan adalah model latar citra pada sistem. Video codec mengkompres video untuk menghasilkan berkas video yang lebih dipadatkan dengan ukuran data yang lebih kecil [5].…”

Section: Analisis Sistemunclassified

Penggunaan Deteksi Gerak untuk Pengurangan Ukuran Data Rekaman Video Kamera CCTV

Sagala

Candradewi

Harjoko

2020

Indonesian J. Electron. Instrum. Syst.

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Some cases the recording data of Closed Circuit Television (CCTV) is stored for future use. In the long term usage, the files size will grow larger and requiring large storage devices. In some cases, the recorded data not only image with the desired object but also the background images that may be recorded for long periods of time. This cases make data storage device usage to be less effective. So this research will design a system of CCTV devices that capable to select images to reduce the size of stored images data by image processing.The images selection of this system is based on based on adaptive median algorithm. When any object get detected, the images data to be saved is current input frame. Otherwise, the data to be saved is background model image. Background model on this system is adapted with the change visual data of background image.The results obtained from this research in the form of a CCTV system that are able to select recording data to be stored with image processing. The background model will be kept adapting with background visual data changes.

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Section: Analisis Sistemunclassified

Penggunaan Deteksi Gerak untuk Pengurangan Ukuran Data Rekaman Video Kamera CCTV

Sagala

Candradewi

Harjoko

2020

Indonesian J. Electron. Instrum. Syst.

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Verification Methodology of Vison Based Hardware Accelerators in System-on-Chip

Khan

Kodavalla

Sameer

2020

2020 International Conference on Industry 4.0 Technology (I4Tech)

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System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Niu¹

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools.Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. viiThe contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods -central bus design and coprocessor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced.Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs.Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption. viii MotivationSince the invention of modern computers from the middle of the twentieth century, semiconductor manufacturers have focused mainly on processing as much information as possible while maintaining or minimizing the execution time. In addition, as technology evolves, the size of the tran...

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System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Cited by 3 publications

References 17 publications

Penggunaan Deteksi Gerak untuk Pengurangan Ukuran Data Rekaman Video Kamera CCTV

Penggunaan Deteksi Gerak untuk Pengurangan Ukuran Data Rekaman Video Kamera CCTV

Verification Methodology of Vison Based Hardware Accelerators in System-on-Chip

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

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