System-on-a-chip test-data compression and decompression architectures based on Golomb codes

Abstract

Abstract-We present a new test-data compression method and decompression architecture based on variable-to-variable-length Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SoC). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. In addition, the novel interleaving decompression architecture allows multiple cores in an SoC to be tested concurrently using a single automatic test equipment input-output channel. We demonstrate the effectiveness of the proposed approach by applying it to the Internaional Symposium on Circuits and Systems' benchmark circuits and to two industrial production circuits. We also use analytical and experimental means to highlight the superiority of Golomb codes over run-length codes.

Test data truncation for test quality maximisation under ATE memory depth constraint

“…For instance, Ichihara et al [20] used statistical codes, Chandra and Chakrabarty [21] made use of Golomb codes, Iyengar et al [22] explored the use of run-length codes, Chandra and Chakrabarty [23] tried frequency-directed run-length codes, and Volkerink et al [24] have investigated the use of Packet-based codes.…”

A compression-driven test access mechanism design approach

“…The approaches analyzed above [5,9,10,16] use TDC methods which are either single-scan chain based [5,10,16] or are not sensitive to the test bus width [9]. Therefore, these compression methods can be added on-top of existing TAM design solutions without any changes to the design flow, and with small performance degradation, in terms of test time and test data, of the compression method.…”

“…In this section we provide an analysis of previous work which focuses on integrated TDC-TAM test solutions [5,9,10,16], considering a control and area-overhead perspective. Previous work analysis for TDC and TAM design are detailed in [12,17] and [8], respectively.…”

“…This mechanism can be an interleaving architecture as illustrated in [5], a distributed architecture as proposed in [10], or a time multiplexing scheme [16]. In all the cases [5,10,16] the distribution mechanism has the external TAM of width much smaller than the internal TAM; for example 1 : n (for n cores) in [5,10]. However, since each core is provided with a decoder, for a large number of cores the area and control overhead is considerable.…”

“…TDC has been approached from a number of research directions. For example, methods which (i) exploit the sparseness of care bits in the test set have been proposed in [2,6,17], and methods which (ii) exploit the regularities within the test set have been proposed in [5,12,18,21].…”