System-on-chip oriented fault-tolerant sequential systems implementation methodology

Pontarelli, Salvatore; Cardarilli, G.C.; Malvoni, A.; Ottavi, Marco; Re, M.; Salsano, A.

doi:10.1109/dftvs.2001.966799

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…• The first method is used by the Atmel AT40K FPGA, [7] and allows to identify the resources of the FPGA to be reprogrammed using a set of control registers. The control registers select the row and the column of the resource to be reconfigured.…”

Section: Fpga Architecture and Fault Modelmentioning

confidence: 99%

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Analysis and Evaluations of Reliability of Reconfigurable FPGAs

et al. 2008

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Many techniques have been proposed in the technical literature for repairing FPGAs when affected by permanent faults. Almost all of these works exploit the dynamic reconfiguration capabilities of an FPGA where a subset of the available resources is used as spares for replacing the faulty ones. The choice of the best reconfiguration technique depends on both the required reliability and on the architecture of the chosen FPGA . This paper presents a survey of these techniques and explains how the architectural organization of the FPGA affects the choice of a reconfiguration strategy. Subsequently, a framework is proposed for these techniques by which a fair comparison among them can be assessed and evaluated with respect to reliability. A reliability evaluation is provided for different repair strategies. To provide a comparison between these techniques FPGAs of different size are taken into account. Also the relationship between the area overhead and the overall reliability has been investigated. Considerations about time to repair and feasibility of these techniques are provided. The ultimate goal of this paper is therefore to present a state-of-the-art repair techniques as applicable to FPGA and to establish their performance for reliability.

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Section: Fpga Architecture and Fault Modelmentioning

confidence: 99%

“…This reprogramming strategy allows a very fast reprogramming and provides a fine granularity in partial reconfiguration. In [7] this feature is used to realize a tile-based spare allocation for the AT40K FPGA.…”

Section: Fpga Architecture and Fault Modelmentioning

confidence: 99%

Analysis and Evaluations of Reliability of Reconfigurable FPGAs

et al. 2008

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“…The classic way for fault-tolerance FSM design is triple modular redundancy (TMR), where three copies of FSM are concurrently run and the correct output value is determined by voting [16]. Even though TMR may be viewed as a basic N-variant design method, we emphasize that the new N-variant methodology is not a simple replication of the FSMs.…”

Section: Fsmmentioning

confidence: 99%

N-variant IC design

Alkabani

Koushanfar

2008

Proceedings of the 45th Annual Design Automation Conference

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We propose the first method for designing N-variant sequential circuits. The flexibility provided by the N-variants enables a number of important tasks, including IP protection, IP metering, security, design optimization, self-adaptation and fault-tolerance. The method is based on extending the finite state machine (FSM) of the design to include multiple variants of the same design specification. The state transitions are managed by added signals that may come from various triggers depending on the target application. We devise an algorithm for implementing the N-variant IC design. We discuss the necessary manipulations of the added signals that would facilitate the various tasks. The key advantage to integrating the heterogeneity in the functional specification of the design is that we can configure the variants during or post-manufacturing, but removal, extraction or deletion of the variants is not viable. Experimental results on benchmark circuits demonstrate that the method can be automatically and efficiently implemented. Because of its lightweight, N-variant design is particularly well-suited for securing embedded systems. As a proof-of-concept, we implement the N-variant method for content protection in portable media players, e.g., iPod. We discuss how the N-variant design methodology readily enables new digital rights management methods.

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“…At present there are many scientific publications, which cover SoC/SiP testing, diagnosis and repair problems [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][19][20]. The testing and repair problem for the digital system logic components has a special place, because repair of faulty logic blocks is technologically complicated problem.…”

Section: Introductionmentioning

confidence: 99%

Algebra-logical repair method for FPGA logic blocks

Hahanov

Galagan

Olchovoy

et al. 2010

2010 East-West Design &Amp; Test Symposium (EWDTS)

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An algebra-logical repair method for FPGA functional logic blocks on the basis of solving the coverage problem is proposed. It is focused on implementation into Infrastructure IP for system-on-a chip and system-in-package. A method is designed for providing the operability of FPGA blocks and digital system as a whole. It enables to obtain exact and optimal solution associated with the minimum number of spares needed to repair the FPGA logic components with multiple faults.Index termsdigital system, system-on-a chip, system-inpackage, FPGA functional logic blocks.

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System-on-chip oriented fault-tolerant sequential systems implementation methodology

Abstract: This paper presents a design methodology for fault tolerant sequential systems implemented on System on Chip (SoC

Cited by 9 publications

References 4 publications

Analysis and Evaluations of Reliability of Reconfigurable FPGAs

Analysis and Evaluations of Reliability of Reconfigurable FPGAs

N-variant IC design

Algebra-logical repair method for FPGA logic blocks

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