Systematic Design of Analog CMOS Circuits

Abstract

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

“…Equations (14) and (15) describe some of the most important performance metrics of the CSVCO such as oscillation frequency ( f osc ), total power (P), and phase noise (L) [21,43,44].…”

“…In Reference [9] Gaussian process-based regression models were used as surrogate models in Bayesian optimization, although effective, the surrogate is completely-application specific, requiring new models to be generated for each circuit topology and technology. Moreover, in Reference [14] gm/I D method [15] and circuit equations are used for a smart reduction of the search space before optimization using the simulator. Still, all these approaches require a large number of computationally expensive circuit simulations within the optimization loops.…”

Innovative Strategy for Mixer Design Optimization Based on gm/ID Methodology

“…Each table computes a different width-independent figure of merit (FOM), closely linked to the design specifications (e.g., transit frequency, intrinsic gain, transconductance efficiency, current density, and relative capacitances). The design process consists in choosing the inversion level of the MOSFETs so that the figures of merit extracted, and the W/L ratios associated with each transistor are able to meet the required design specifications [6,10]. The g m /I D ratio, also known as the transconductance efficiency or gain-power Electronics 2019, 8, 954 4 of 12 efficiency, is a proxy for the inversion level the transistor.…”

“…In theory, given the symmetry of the circuit, any common-mode RF and LO frequency component at the output should be zero. This paper aims to extend the Jespers and Murmann gm/ID-based approach [5,6] to optimize the design of a double-balanced mixer based on the Gilbert cell. A new set of lookup tables were computed to take into account the performance of the mixer in the three MOSFET inversion regions.…”

“…With these new set of lookup tables, the designer is able to maximize the overall performance of the basic cell without introducing complex circuit solutions. The reported mixer was used in the design of the positioning system reported in [6][7][8][9]. The rest of the paper is arranged as follow.…”