Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

Zhou, Zheng; Shen, Chung-Ching; Plishker, William; Wu, Hsiang-Huang; Bhattacharyya, Shuvra S.

doi:10.1109/icosp.2012.6491686

Cited by 1 publication

(6 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Specifically, we incorporated the TPPF into the TDIF-PPG framework [36] to implement an Image Registration (IR) application [31].…”

Section: Results For Fp-pas Problem On Msmmentioning

confidence: 99%

“…Additionally, the device has 512MB of on board DRAM that can be accessed by "TeraNet". For schedule implementation details, we refer the reader to [36].…”

Section: Methodsmentioning

confidence: 99%

“…[36] is a dataflow-based design flow for design and implementation of parallel software targeted to MPSoC devices. TDIF-PPG extends the capabilities of the Targeted Dataflow Interchange Format (TDIF) [26] design environment with methods, based on a model called the Parallel Processing Group (PPG), for expressing intra-actor parallelism, and associated capabilities for platform independent design, and early-stage performance evaluation.…”

Section: Dataflow Interchange Formatmentioning

confidence: 99%

“…Layer 2 is the actor interface layer: actor interface specifications, including information about input and output ports, actor parameters, and CFDF modes for individual actors are provided using the TDIF language. Layer 3 is the Platform-Independent Mode Specification (PIMS) layer: the Parallel Processing Group (PPG) model [36] guides the programmer in exposing actor level parallelism within the functional specification for each mode of an actor. Layer 4 is the actor implementation layer: generic actor specifications from the PIMS layer are integrated with optimized platform-specific PPG API and run-time implementations.…”

Section: Tdif-ppgmentioning

confidence: 99%

“…Following the terminology in [36], we refer to an actor whose execution requires a mapping to a unique processing element as an Sequential Actor (SA). By contrast, a Parallel Actor (PA) is an actor that embeds inner (intrafiring) parallelism, and whose execution may be accelerated by use of multiple processing elements.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing

Zhou

Plishker

Bhattacharyya

et al. 2014

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

International audienceParallelization of Digital Signal Processing (DSP) software is an important trend in Multiprocessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous Dataflow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We first address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized are parallel actors (i.e., they can be parallelized to exploit multiple cores). For this special case, we develop and experimentally evaluate a two-phase scheduling framework with three work flows that involve particle swarm optimization (PSO) — PSO with a mixed integer programming formulation, PSO with simulated annealing, and PSO with a fast heuristic based on list scheduling. Then, we extend our scheduling framework to support the general PAS problem, which considers both parallel actors and sequential actors (actors that cannot be parallelized) in an integrated manner. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions. We also demonstrate the performance of our scheduling framework from two aspects: simulations on a diverse set of randomly generated SDF graphs, and implementations of an image processing application and a software defined radio benchmark on a state-of-the-art multicore DSP platform

show abstract

“…Specifically, we incorporated the TPPF into the TDIF-PPG framework [36] to implement an Image Registration (IR) application [31].…”

Section: Results For Fp-pas Problem On Msmmentioning

confidence: 99%

“…Additionally, the device has 512MB of on board DRAM that can be accessed by "TeraNet". For schedule implementation details, we refer the reader to [36].…”

Section: Methodsmentioning

confidence: 99%

Section: Dataflow Interchange Formatmentioning

confidence: 99%

Section: Tdif-ppgmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations