Systematic methodology for designing low power direct digital frequency synthesisers

Design and implementation of a DDS‐based multi‐carrier GMSK modulator

“…sin(x)− g(x)−q(x)), we can reduce more the memory size (reducing amplitude of the samples). This algorithm achieves higher compression levels, regardless of the length of the accumulator being increased (number of N bits) [9].…”

“…This truncation of phase bits introduces spurious signals in the output spectrum of the DDS. In this paper, a technique developed in [9] is adopted for implementing the DDS. This technique exploits certain properties of the existing algorithms and modifies them properly, achieving better compression ratios of ROM.…”

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

“…And the accuracy and stability is determined by quartz [2]. More vibration-mixing circuits can be used to get a wider frequency range as shown in Figure 1.…”

“…It focuses on the improvement of frequency accuracy and compression of memory capacity. It's proved that with the improvement of structure and the introduction of new algorithms, the compression of memory capacity is achieved without damaging the system speed and stability [2,3].…”

Design of direct digital frequency synthesizers based on unilateral second-order approximations

“…The most critical stage in a DDFS is the PSAC. Many prior works for improving the performance of PSAC include angular decomposition techniques [1,[3][4][5][6], angle rotation methods [7][8][9], polynomial approximations [10][11][12], and sine amplitude compression methods [13][14][15][16]. In the sine amplitude compression methods, they only use linear approximations to decrease a ROM size.…”