SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments

Weinstock, Jan Henrik; Leupers, Rainer; Ascheid, Gerd; Petras, Dietmar; Hoffmann, Andreas

doi:10.3850/9783981537079_0114

Cited by 11 publications

(4 citation statements)

References 12 publications

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“…Each cluster manages its own local time and synchronizes with the others through timestamped messages. Other similar approaches have been proposed such as [16] where the clusters are connected through channels with latencies. It allows a cluster to run ahead of its neighbours without risking to receive a message from the past.…”

Section: Related Work a Parallel Systemc Approachesmentioning

confidence: 99%

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Busnot

Sassolas

Ventroux

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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To face the growing complexity of System-on-Chips (SoCs) and their tight time-tomarket constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC kernel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).

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Section: Related Work a Parallel Systemc Approachesmentioning

confidence: 99%

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Busnot

Sassolas

Ventroux

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

View full text Add to dashboard Cite

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“…In [9] the authors studied the distributed parallel simulation, where SystemC models are organized into small executable units and distributed onto different host machines to run in parallel. [10] provides a parallel SystemC simulation kernel which requires the user to manually translate the sequential design into a safe parallel design. [11] takes a survey about existing SystemC simulation approaches and concludes that most of these works do not fully support the parallel simulation of TLM-2.0 LT models due to shared variables.…”

Section: Related Workmentioning

confidence: 99%

Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models

Cheng

Dömer

2019

ACM Trans. Embed. Comput. Syst.

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The SystemC TLM-2.0 standard is widely used in modern electronic system level design for better interoperability and higher simulation speed. However, TLM-2.0 has been identified as an obstacle for parallel SystemC simulation due to the disappearance of channels. Without a containment construct, simulation threads are permitted to directly access data of other modules and that makes it difficult to synchronize such accesses as required by the SystemC execution semantics. In this paper, we propose a compile time approach to statically analyze potential conflicts among threads in SystemC TLM-2.0 loosely- and approximately-timed models. We introduce a new Socket Call Path technique which provides the compiler with socket binding information for precise static analysis. We also propose an algorithm to analyze entangled variable pairs. Experimental results show that our approach is able to support automatically safe parallel simulation of SystemC models with TLM-2.0 Blocking Transport Interface, Direct Memory Interface and Non-blocking Transport Interface, resulting in impressive simulation speeds.

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“…Finally, in [36] ,SystemC-Link, a simulation framework for SystemC simulators, is presented. It is an overlay above SystemC kernels, which allows the use of different versions of a SystemC kernel in one simulation.…”

Section: Distributed Time/relaxing Synchronizationsmentioning

confidence: 99%

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

2016

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Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level.

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SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments

Cited by 11 publications

References 12 publications

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models

Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

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