Systolic inner product arrays with automatic word rounding

Yan, M.; Canny, J. V. Mc

doi:10.1007/bf00925124

Cited by 4 publications

(5 citation statements)

References 8 publications

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“…Overall system wordlength is then reduced by (m-1) bits and this produces a proportional increase in data throughput rate. The main hardware costs incurred are slightly more complex cells and a slightly greater latency [16] [20]. It should be noted that for all the VQ systems presented in this paper the ARIPA circuits are interchangeable with IPA building block circuits and are an attractive alternative if lower precision is permitted in specific applications.…”

Section: = Latchmentioning

confidence: 97%

“…Furthermore, as has been shown section 4.1.2, IPA system word growth can be reduced greatly by using ARIPA circuits, albeit at the cost of small amount of additional hardware. The Area-Time (AT) performance of such ARIPA circuits is in general considerably better than similar bit serial architectures [20]. Whilst a bit parallel systems are perhaps more flexible in terms of handling word growth (i.e.…”

Section: Suitability Of the Bit Serial Approach To The Design Of Vq Smentioning

confidence: 99%

“…It can be seen that the format of the partial results emerging from the main array is directly compatible with that required by the accumulator circuit. Further details of the operation of this circuit have been presented in references [ 16] and [20].…”

Section: = Latchmentioning

confidence: 99%

See 2 more Smart Citations

VLSI architectures for vector quantization

Yan¹,

McCanny²,

Hu³

1995

Journal of VLSI Signal Processing

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Abstract. The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for VQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for VQ implementations in terms of performance and cost.

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Section: = Latchmentioning

confidence: 97%

Section: Suitability Of the Bit Serial Approach To The Design Of Vq Smentioning

confidence: 99%

See 1 more Smart Citation

VLSI architectures for vector quantization

Yan¹,

McCanny²,

Hu³

1995

Journal of VLSI Signal Processing

Self Cite

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“…In this paper, we propose a bit-serial architecture computing the DWT. The bit-serial processing mode has been largely adopted in DSP ASIC's (e.g., [16]- [25]) since it has many advantages with respect to the parallel approach [26], such as a simpler communication strategy (single wires instead of data-buses), a reduced number of pins, lower power requirement, less hardware complexity, and the possibility of achieving very high throughput by pipelining at the bit level. Moreover, the bit-serial approach often allows internal regular structures which are suitable for VLSI implementation.…”

Section: Introductionmentioning

confidence: 99%

“…The removal (total or partial) of "wait-cycles" between two consecutive input samples is a key for increasing the achievable throughput in bit-serial signal processors. In this context, some convolvers have been already designed [20]- [25]. Here, we introduce the first (on the best of our knowledge) architecture which totally avoids the need of wait cycles in the DWT bit-serial computation.…”

Section: Introductionmentioning

confidence: 99%

A "double-face" bit-serial architecture for the 1D discrete wavelet transform

Marino

2000

IEEE Trans. Circuits Syst. II

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We propose a novel discrete wavelet transform (DWT) architecture which is fully scalable, flexible, and modular. This architecture is bit serial, and therefore, has low hardware complexity and low power requirement. Nevertheless, because of its particular structure, it operates on-the-fly (i.e., it does not require wait cycles between consecutive input samples). Moreover, a very small hardware overhead can upgrade the architecture to compute also the inverse DWT ("double-face" utilization). Hardware complexity and computing performance are analyzed in detail.

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A two-level interleaving architecture for serial convolvers

Marino

1999

IEEE Trans. Signal Process.

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In this correspondence, we present a bit-serial architecture for convolving/correlating long numerical sequences by long filter functions. Because of its two-level interleaving structure, the proposed device does not require "wait cycles" between consecutive input samples. As a result, it achieves the highest possible throughput. Cascadability, fault tolerance, feasibility in VLSI technology, and computing performances are discussed and analyzed.

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Systolic inner product arrays with automatic word rounding

Cited by 4 publications

References 8 publications

VLSI architectures for vector quantization

VLSI architectures for vector quantization

A "double-face" bit-serial architecture for the 1D discrete wavelet transform

A two-level interleaving architecture for serial convolvers

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