Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution

Niras, C. V.; Thomas, Vineetha

doi:10.1109/ised.2012.47

Cited by 3 publications

(7 citation statements)

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“…The other two designs are different from those in Table 9 in that they use a higher radix [39] or a pipelined FFT [40] (single-path delay feedback) architecture to reduce the overall number of cycles needed to compute a DFT in less than the actual transform size N. This means it is possible to have a streaming architecture, e.g., one where data flows continuously into and out of the circuit (Fmax is the same as the sample rate).…”

Section: Other Fpga Lte Implementationsmentioning

confidence: 99%

“…To compute high performance run-time transforms for N = 2 n , a variety of mixed radix approaches have been proposed [38][39][40][41]. The performance of the different designs is primarily related to the complexity of the butterfly unit design.…”

Section: Related Workmentioning

confidence: 99%

“…The other designs are different from those discussed above in that they either use a higher radix memory-based design [39] or a pipelined architecture [40] to reduce the overall number of cycles needed to compute a DFT to less than the actual transform size N.…”

Section: Related Workmentioning

confidence: 99%

“…No SQNR data was supplied to indicate the circuit precision, although the internal precision in [39] was 18-bits and [40] used a mixed floating point (the same exponent for real and imaginary words) and block floating point. Details regarding latency are not discussed in these papers; however, comparison is still instructive and performance can be estimated based on throughput alone, which is more important than latency for computing resource blocks.…”

Section: Other Fpga Lte Implementationsmentioning

confidence: 99%

“…For the DMBA, the average throughput as a function of N for all 35 transform sizes is 2.1N, which is a factor of two higher than the other implementations. However, these more complex architectures require far more LUT hardware, 2.7 times and 3.7 times for [39] and [40], respectively. Although [40] uses fewer registers, this is less meaningful because the 10:1 ratio of LUTs:registers in FPGA hardware leads to imbalances that can cause many registers to be inaccessible.…”

Section: Other Fpga Lte Implementationsmentioning

confidence: 99%

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Distributed-Memory-Based FFT Architecture and FPGA Implementations

Nash¹

2018

Electronics

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A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

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Section: Other Fpga Lte Implementationsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%