t-TDA-diagnosable systems

Chu, Shanbo; Armstrong, J. R.

doi:10.1109/12.24306

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1991

1992

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Fault tolerance of on‐board digital signal processing circuits

Raghunandan¹,

Coakley²,

Evans³

1991

Int. J. Satell. Commun.

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The paper is organized in four sections. The first section introduces the nature of faults as well as their causes. The methods used to identify faults and the actions necessary to correct the situation are outlined. The second section identifies the different fault tolerance approaches to conventional computational circuits and the DSP circuits. Current research work in the area of fault tolerance of FFT, signal processing and VLSI circuits involving systolic arrays is reviewed. Since some of the techniques do not involve error correction, reconfiguration of the circuit after error detection becomes necessary and a brief look at the relevant reconfiguration strategies is appropriate. Software fault tolerance is introduced and some work applicable to computations in general is reviewed. The implementation of the methods and its consequences are described in the third section. Concluding remarks form the final section. KEY WORDS Coding Digital signal processing Fault tolerance FFT Residue number systems Reconfiguration Satellite communication Software and hardware reliability Systolic arrays VLSI

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