Fault tolerance of on‐board digital signal processing circuits

Abstract

The paper is organized in four sections. The first section introduces the nature of faults as well as their causes. The methods used to identify faults and the actions necessary to correct the situation are outlined. The second section identifies the different fault tolerance approaches to conventional computational circuits and the DSP circuits. Current research work in the area of fault tolerance of FFT, signal processing and VLSI circuits involving systolic arrays is reviewed. Since some of the techniques do not involve error correction, reconfiguration of the circuit after error detection becomes necessary and a brief look at the relevant reconfiguration strategies is appropriate. Software fault tolerance is introduced and some work applicable to computations in general is reviewed. The implementation of the methods and its consequences are described in the third section. Concluding remarks form the final section. KEY WORDS Coding Digital signal processing Fault tolerance FFT Residue number systems Reconfiguration Satellite communication Software and hardware reliability Systolic arrays VLSI

Fault tolerant onboard packet switch architecture for communication satellites - Shared memory per beam approach

“…The shared memory per beam packet switch will be implemented using fault tolerance techniques such as fault avoidance, fault detection, fault correction, redundancy, and reconfiguration. 3 Critical portions of the design, those most susceptible to failure and those whose failure would cause the most problems, will first be identified. Fault tolerant design and special manufacturing techniques will then be used.…”