T4P4S: A Target-independent Compiler for Protocol-independent Packet Processors

Vörös, Péter; Horpácsi, Dániel; Kitlei, Róbert; Leskó, Dániel; Tejfel, Máté; Laki, Sándor

doi:10.1109/hpsr.2018.8850752

Cited by 40 publications

(17 citation statements)

References 7 publications

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“…Here the actions are a collection of protocol‐independent primitives. Architectural design and approach Voros et al proposed a compiler called T4P4S 16 considering multiple targets. T4P4S generates a high‐performance switching program using the P4 definition.…”

Section: Data Plane Programmingmentioning

confidence: 99%

Packet processing and data plane program verification: A survey with tools, techniques, and challenges

Akarte

Yadav

2023

Int J Communication

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SummaryIn today's era of fast‐growing network‐enabled devices combined, it increases the complexity of the network. This leads to the massive data packet transfer on the network via the data plane in a software‐defined networking environment. The programmable packet processing in a data plane may introduce indirect bugs that are hard to catch manually. To avoid catastrophic after‐effects, such programs need to be formally verified. Researchers have proposed various tools and techniques to verify the data plane program using the P4 language. Most of the researchers have used the concept of assertion and symbolic execution to provide P4 verification approaches. As symbolic execution does not scale up well, researchers have proposed different techniques, which include the use of constraints, slicing of the program, parallelization, data plane verification, program verification, and so on. The tools have experimented with different choices for compiler optimization. In this article, we perform a pervasive survey on various verification tools and techniques based on data plane programming using domain‐specific language like P4 from the inception of the concept. We have compared the packet processing tools developed as per the requirement of time with their ideology and the impact of change.

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Section: Data Plane Programmingmentioning

confidence: 99%

Packet processing and data plane program verification: A survey with tools, techniques, and challenges

Akarte

Yadav

2023

Int J Communication

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“…Target-independency means that P4 program can run on various targets such as hardware targets (switch and routers), and software targets such as BMv2 P4-OvS, and P4-DPDK [12], and number of supported targets are increasing. To ensure this feature, the hardware vendor or data plane language developers must define architecture and a compiler backend for a given target: provide them to the P4 developer [13] and so, the P4 program is easily mapped to the target with help of these. Protocol independency means that P4 developers can define their rich set of protocols and data plane behaviour/functionalities.…”

Section: P4 Languagementioning

confidence: 99%

Untitled

2022

IJDPS

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By programming both the data plane and the control plane, network operators can adapt their networks to their needs. Thanks to research over the past decade, this concept has more formulized and more technologically feasible. However, since control plane programmability came first, it has already been successfully implemented in the real network and is beginning to pay off. Today, the data plane programmability is evolving very rapidly to reach this level, attracting the attention of researchers and developers: Designing data plane languages, application development on it, formulizing software switches and architecture that can run data plane codes and the applications, increasing performance of software switch, and so on. As the control plane and data plane become more open, many new innovations and technologies are emerging, but some experts warn that consumers may be confused as to which of the many technologies to choose. This is a testament to how much innovation is emerging in the network. This paper outlines some emerging applications on the data plane and offers opportunities for further improvement and optimization. Our observations show that most of the implementations are done in a test environment and have not been tested well enough in terms of performance, but there are many interesting works, for example, previous control plane solutions are being implemented in the data plane.

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“…In [11] the forwarding latency of three P4-based network functions is estimated by adding the latency cost of their constituting atomic P4 constructs. The estimations were then validated against the real measured latency when running these three programs on three different P4 devices: (i) An Agilio CX 2x10GbE SmartNIC from Netronome, which is a Network Processor Unit (NPU)-based NIC with tens of multi-threaded cores that support an instruction set architecture optimized for packet processing [14]; (ii) A NetFPGA-SUME board with Xilinx Virtex-7 XC7V690T FFG1761-3 FPGA [15], which is an FPGA-based packet processor optimized to make use of FPGA programmability while maintaining high packet processing performance; (iii) An open-source T4P4S DPDKbased P4 software switch [16], which is a software switch that can run on commodity servers while leveraging the DPDK framework for optimizing packet processing on CPUs. The three programs, which have increasing complexity, are Layer 3 Forwarding (L3FWD), Layer 3 Forwarding with Firewall filtering (L3FWD + Firewall), and VxLAN Decapsulation (VxLAN).…”

Section: Model Evaluationmentioning

confidence: 99%

Modeling and Performance Analysis of P4 Programmable Devices

Harkous

Kröger

Jarschel

et al. 2021

2021 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN)

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In our digitized society, emerging applications require highly performant and flexible networks that can adapt to satisfy varying connectivity needs. P4 as a domain-specific programming language for data plane pipelines introduces the required flexibility through easy-to-use programmability. However, the performance of P4-capable devices is still an open question that has not yet been completely addressed. Understanding whether a P4-enabled device can meet the performance requirements for a specific network function pipeline is key for planning as well as deployment scenarios in a communication provider network.In this paper, we propose a simple analytical model that can quickly predict the performance of network functions written in P4 for a given device. The programmable data plane of P4 devices is modeled as a forward queuing system with a variable service rate that depends on the complexity of the configured data path program. On top of the data plane model, the controller's interaction is modeled as a feedback queuing system. We evaluate the accuracy of our model through a parameter study and simulation. The evaluation reveals corner cases, which are analyzed to formalize a constraint on the service rate using model parameters to guarantee stable system performance.

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T4P4S: A Target-independent Compiler for Protocol-independent Packet Processors

Cited by 40 publications

References 7 publications

Packet processing and data plane program verification: A survey with tools, techniques, and challenges

Packet processing and data plane program verification: A survey with tools, techniques, and challenges

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Modeling and Performance Analysis of P4 Programmable Devices

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