Data plane programmability brings network flexibility to a new level. However, it introduces the complexity of the data path's program as a new factor that influences packet forwarding latency and thus devices' performance. Accurate identification of the relation between data path complexity and packet forwarding latency enables the design and management of networks with predictable performance.In this paper, we leverage the characteristics of P4 programming language to provide a method for estimating the packet forwarding latency as a function of the data path program. We analyze the impact of different P4 constructs on packet processing latency for three state-of-the-art P4 devices: Netronome SmartNIC, NetFPGA-SUME, and T4P4S DPDK-based software switch. Besides comparing the performance of these three targets, we use the derived results to propose a method for estimating the average packet latency, at compilation time, of arbitrary P4-based network functions implemented using the surveyed P4 constructs. The proposed method is finally validated using a set of realistic network functions, which shows that our method estimates the average packet latency with sub-microsecond precision.

In our digitized society, emerging applications require highly performant and flexible networks that can adapt to satisfy varying connectivity needs. P4 as a domain-specific programming language for data plane pipelines introduces the required flexibility through easy-to-use programmability. However, the performance of P4-capable devices is still an open question that has not yet been completely addressed. Understanding whether a P4-enabled device can meet the performance requirements for a specific network function pipeline is key for planning as well as deployment scenarios in a communication provider network.In this paper, we propose a simple analytical model that can quickly predict the performance of network functions written in P4 for a given device. The programmable data plane of P4 devices is modeled as a forward queuing system with a variable service rate that depends on the complexity of the configured data path program. On top of the data plane model, the controller's interaction is modeled as a feedback queuing system. We evaluate the accuracy of our model through a parameter study and simulation. The evaluation reveals corner cases, which are analyzed to formalize a constraint on the service rate using model parameters to guarantee stable system performance.

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P4 programmable data planes are becoming more popular due to the flexibility they provide in describing the packet processing pipeline. P4 successfully abstracts the processing pipeline of data planes using a limited set of constructs. The performance variation as a function of the configured P4 pipeline is an important aspect that should be studied. Analyzing the impact of different P4 constructs on packet latency helps in understanding the overall performance of P4 programmable devices. In this paper, we analyze the impact of a basic set of P4 constructs on packet processing latency to derive the influential parameters. We use the derived results to propose a method for estimating the packet latency of P4-based network functions implemented using the surveyed P4 constructs. Finally, we validate the accuracy of the proposed method by applying it to realistic network functions.