Taming the IXP network processor

George, Lal; Blume, M.

doi:10.1145/780822.781135

Cited by 17 publications

(7 citation statements)

References 21 publications

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“…Commercial offerings in the past such as Intel IXP [3] and IBM PowerNP [11] were also specialized for network flow processing. Nova [21] and Shangri-La [16] develop programming languages and compilers for Intel IXP network processors. The recent resurgence of SmartNICs is closely related to these earlier efforts in network processor architectures.…”

Section: Related Workmentioning

confidence: 99%

Clara

Qiu

Kang

Liu

et al. 2020

Proceedings of the 19th ACM Workshop on Hot Topics in Networks

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The gap between CPU and networking speeds has motivated the development of SmartNICs for near-network processing. Recent work has shown that many network functions can benefit from Smart-NIC offloading, but identifying the best porting strategy requires hand-tuning and workload-specific optimizations. The developer has no easy way to understand the ported performance beforehand. We are developing a tool called Clara, whose goal is to provide performance clarity for SmartNIC offloading. Clara can analyze an unported NF in its original form, and predict its performance when ported to a SmartNIC target. This automated workflow enables the developer to easily customize offloading strategies, obtain performance insights, and identify suitable SmartNIC models for her workloads. Clara's key technical roadmap is to emulate a compiler, lowering an unported program to a SmartNIC target logically, without performing code generation. This results in a mapping from core NF logic to SmartNIC hardware resources, and Clara then plugs in NIC parameters to predict the performance for specific workloads. We describe our progress so far, and report initial validation results with Netronome hardware.

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Section: Related Workmentioning

confidence: 99%

Clara

Qiu

Kang

Liu

et al. 2020

Proceedings of the 19th ACM Workshop on Hot Topics in Networks

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“…Click [66] uses C++ for packet processing on software routers. NOVA [56], packetC [47], Intel's auto-partitioning C compiler [44], Pa-cLang [48,49], and Microengine C [16, 18] target network processors [19,20]. Domino's C-like syntax and sequential semantics are inspired by these DSLs.…”

Section: Related Workmentioning

confidence: 99%

“…For such algorithms, it is important for programmability to directly capture the algorithm's intent without requiring it to be "shoehorned" into hardware constructs such as a sequence of match-action tables. Indeed, this is how such data-plane algorithms are expressed in pseudocode [53,92,3,67,52], and implemented in software routers [66,11,46], network processors [47,56], and network endpoints [8].…”

Section: Introductionmentioning

confidence: 99%

Packet Transactions: High-level Programming for Line-Rate Switches

Sivaraman¹,

Budiu²,

Cheung³

et al. 2015

Preprint

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Many algorithms for congestion control, scheduling, network measurement, active queue management, security, and load balancing require custom processing of packets as they traverse the data plane of a network switch. To run at line rate, these data-plane algorithms must be in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built.This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chipsets. The key challenge is that these algorithms create and modify algorithmic state.The key idea to achieve line-rate programmability for stateful algorithms is the notion of a packet transaction: a sequential code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient and natural way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated die-area overhead.

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“…For Bodik's e-SSA [6] we have Defs ↓ Out(Conds) ↓ . Finally, for SSU [22,27,34] we have Uses ↑ . The SSI constrained system might have several inequations for the same left-hand-side, due to the way we insert phi and sigma functions.…”

Section: Our Approach Vs Other Sparse Evaluation Frameworkmentioning

confidence: 99%

“…The Static Single Assignment (SSA) form [16], for instance, allows us to implement several analyses and optimizations, such as reaching definitions and constant propagation, sparsely. Since its conception, the SSA format has been generalized into many different program representations, such as the Extended-SSA form [6], the Static Single Information (SSI) form [2], and the Static Single Use (SSU) form [22,27,34]. Each of these representations extends the reach of the SSA form to sparser data-flow analyses; however, there is not a format that subsumes all the others.…”

Section: Introductionmentioning

confidence: 99%

Parameterized Construction of Program Representations for Sparse Dataflow Analyses

Tavares¹,

Boissinot²,

Pereira³

et al. 2014

Lecture Notes in Computer Science

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Abstract. Data-flow analyses usually associate information with control flow regions. Informally, if these regions are too small, like a point between two consecutive statements, we call the analysis dense. On the other hand, if these regions include many such points, then we call it sparse. This paper presents a systematic method to build program representations that support sparse analyses. To pave the way to this framework we clarify the bibliography about well-known intermediate program representations. We show that our approach, up to parameter choice, subsumes many of these representations, such as the SSA, SSI and e-SSA forms. In particular, our algorithms are faster, simpler and more frugal than the previous techniques used to construct SSI -Static Single Information -form programs. We produce intermediate representations isomorphic to Choi et al.'s Sparse Evaluation Graphs (SEG) for the family of data-flow problems that can be partitioned per variables. However, contrary to SEGs, we can handle -sparsely -problems that are not in this family. We have tested our ideas in the LLVM compiler, comparing different program representations in terms of size and construction time.

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Taming the IXP network processor

Cited by 17 publications

References 21 publications

Clara

Clara

Packet Transactions: High-level Programming for Line-Rate Switches

Parameterized Construction of Program Representations for Sparse Dataflow Analyses

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