TAMPER: Thermal Assistant Method to Improve Write PERformance in STT-RAM Memories

Faraji, Saeed Seyed; Hajisadeghi, Amir M.; Zarandi, Hamid-Reza

doi:10.1109/iraniancee.2019.8786621

Cited by 1 publication

(3 citation statements)

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“…11-15, these temperatures lead to a decrease in the overall write latency of the circuit. The exact value for VDDL is equal to 0.86001v and calculated by considering the VDDH of the circuit, total power consumption, and latency overwriting "logic-zero" as optimization parameters [11]. The circuits are simulated under various process corners, and it turns out that our circuit is immune to process variation.…”

Section: B Circuit Evaluationmentioning

confidence: 99%

“…STT-RAM is equipped with an MTJ device composed of three layers (pinned/up, thin barrier/middle, free/down) [11]. Read and write operations are carried out by applying currents smaller and larger than the critical switching current (IC) across the MTJ.…”

Section: Reliability Challenges In Stt-rammentioning

confidence: 99%

“…STT-RAM is highly sensitive towards temperature, and even a slight change in the room temperature can significantly impact the rotation process, as studied in [10]. Thermallyassisted switching or thermal-controlled magnetic anisotropy (TCMA) exerts trade-off write time and write energy [11]. Thus, considering the thermal effect on the switching process can improve write energy and write time.…”

Section: Introductionmentioning

confidence: 99%

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EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit

et al. 2022

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Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density. Its magnetic properties have a vital role in STT switching operations through thermal effectiveness. A key challenge for STT-RAM in industrial adaption is the high write energy and latency. In this paper, we overcome this challenge by exploiting the stochastic switching of STT-RAM cells and, in tandem, with circuit-level approximation. We enforce the robustness of our technique by analyzing the vulnerability of write operation against radiation-induced soft errors and applying a low-cost improvement. Due to serious reliability challenges in nanometer-scale technology, the robustness of the proposed circuit is also analyzed in the presence of CMOS and magnetic tunnel junction (MTJ) process variation. Compared to the state-of-the-art, we achieve 33.04% and 5.47% lower STT-RAM write energy and latency, respectively, with a 3.7% area overhead, for memory-centric applications.

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Section: B Circuit Evaluationmentioning

confidence: 99%

Section: Reliability Challenges In Stt-rammentioning

confidence: 99%