Tapered Cross Section Photoelectron Spectroscopy Provides Insights into the Buried Interfaces of III‐V Semiconductor Devices

Abstract

Interfaces are key elements that define electronic properties of the final device. Inevitably, most of the active interfaces of III–V semiconductor devices are buried and it is therefore not straightforward to characterize them. The Tapered Cross Section Photoelectron Spectroscopy (TCS‐PES) approach is promising to address such a challenge. That the TCS‐PES can be used to study the relevant heterojunction in epitaxial III–V architectures prepared by metalorganic chemical vapor deposition is demonstrated here. A MULTIPREP polishing system that enables controlling the angle between the sample holder and the polishing plate has been employed to improve the reproducibility of the polishing procedure. With this procedure, that preparing the TCS of III–V semiconductor devices with tapering angles lower than 0.02° is possible is demonstrated. The PES provides then information about the buried interfaces of Ge|GaInP and GaAs|GaInP layer stacks. Both, chemical and electronic properties have been measured by PES. It evidences that the preparation of the TCSs under an uncontrolled atmosphere modifies the pristine properties of the critical buried heterointerfaces. Surface states and reaction layers are created on the TCS surface, which restrict unambiguous conclusions on buried interface energetics.

Unraveling the Energetic Landscape of Perovskite Solar Cells: A Synergy of 2D Drift‐Diffusion Simulations and Tapered Cross‐Section Photoelectron Spectroscopy

“…However, performing PES on these interfaces requires accessing them without modifying the characteristics of the device. [ 6 ] Accessing the interfaces by preparation and investigation of a normal cross section is not feasible due to low lateral resolution of standard PES set‐up (i.e., above 10 μm and up to several hundreds of micrometers) compared with the thickness of typical perovskite solar cells and especially with the extensions of the space charge regions within. Approaches to overcome this limitation exist and can be classified as bottom‐up or top‐down approaches.…”

“…This was the case for III‐V semiconductor devices (e.g., GaInP on Ge and GaAs substrates) that were strongly disturbed by Fermi‐level pinning to the surface states created by the polishing procedure, also rendering it impossible to measure binding energy shifts due to illumination. [ 6 ] In contrast, perovskites with their shallow gap states are unaffected by this phenomenon and previous works have shown that it is possible to extract reliable information on the electronic properties of PSCs. [ 25 ] Moreover, the binding energies observed in TCS layers, along with their change under illumination, are in good agreement with previous measurements from half‐cells that were not subjected to the TCS‐preparation method.…”

“…So far, TCS has been prepared with a metallographic polishing machine, a drilling machine or ultra-low-angle microtomy. [6,20,21,22,[23][24][25] The essential condition for utilizing the binding energy variation at the interfaces on the TCS to infer the band diagram of the entire device is, that the TCS preparation process should not alter it. Surface states created on the TCS may induce band bending toward the TCS as artifacts and disturb the band bending along the device.…”