Interfaces are key elements that define electronic properties of the final device. Inevitably, most of the active interfaces of III–V semiconductor devices are buried and it is therefore not straightforward to characterize them. The Tapered Cross Section Photoelectron Spectroscopy (TCS‐PES) approach is promising to address such a challenge. That the TCS‐PES can be used to study the relevant heterojunction in epitaxial III–V architectures prepared by metalorganic chemical vapor deposition is demonstrated here. A MULTIPREP polishing system that enables controlling the angle between the sample holder and the polishing plate has been employed to improve the reproducibility of the polishing procedure. With this procedure, that preparing the TCS of III–V semiconductor devices with tapering angles lower than 0.02° is possible is demonstrated. The PES provides then information about the buried interfaces of Ge|GaInP and GaAs|GaInP layer stacks. Both, chemical and electronic properties have been measured by PES. It evidences that the preparation of the TCSs under an uncontrolled atmosphere modifies the pristine properties of the critical buried heterointerfaces. Surface states and reaction layers are created on the TCS surface, which restrict unambiguous conclusions on buried interface energetics.

Interfaces are key elements that define electronic properties of the final device. Inevitably, most of the active interfaces of III-V semiconductor devices are buried and it is therefore not straightforward to characterize them. The Tapered Cross-Section Photoelectron Spectroscopy (TCS-PES) approach is promising to address such a challenge. We demonstrate here that the TCS-PES can be used to study the relevant heterojunction in epitaxial III-V architectures prepared by metalorganic chemical vapor deposition. A MULTIPREPTM polishing system that enables controlling the angle between the sample holder and the polishing plate has been employed to improve the reproducibility of the polishing procedure. With this procedure, we demonstrate that preparing the TCS of III-V semiconductor devices with tapering angles lower than 0.02° is possible. The PES provides then information about the buried interfaces of Ge|GaInP and GaAs|GaInP layer stacks. Both, chemical and electronic properties have been measured by PES. It evidences that the preparation of the TCSs under an uncontrolled atmosphere modifies the pristine properties of the critical buried heterointerfaces. Surface states and reaction layers are created on the TCS surface, which restrict unambiguous conclusions on buried interface energetics.

Interfaces are key elements that define electronic properties of the final device. Inevitably, the active interfaces of III-V semiconductor devices are buried and it is therefore not straightforward to characterize them. The Tapered Cross-Section Photoelectron Spectroscopy (TCS-PES) approach is a promising method to address such a challenge. For the first time, we demonstrate the TCS-PES on III-V architectures. A MULTIPREPTM polishing system that enables controlling the angle between the sample holder and the polishing plate has been employed to improve reproducibility of the polishing procedure. With such equipment, we demonstrate that preparing the TCS of III-V semiconductor devices with tapering angles lower than 0.02° is possible. The TCS-PES provides then information about the buried interfaces of Ge|GaInP and GaAs|GaInP layer stacks, prepared by metalorganic chemical vapor deposition (MOCVD). Both, chemical and electronic properties have been measured by PES. It evidences that the preparation of the TCSs under an uncontrolled atmosphere modifies the pristine properties of the critical buried heterointerfaces. Surface states and reaction layers are created on the TCS surface, which restrict unambiguous conclusions on buried interface energetics.