Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

Chatterjee, Navonil; Paul, Suraj; Chattopadhyay, Santanu

doi:10.1016/j.sysarc.2018.01.002

Cited by 31 publications

(16 citation statements)

References 23 publications

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“…The authors in [23] proposed the idea of using two different types of PEs, i.e., special purpose and general-purpose PEs. The objective of the work is to achieve a transient fault aware mapping and scheduling (TFAMS) scheme that satisfies the deadline requirement of task as well as minimizes energy consumption during allocation.…”

Section: Related Workmentioning

confidence: 99%

“…Moreover, communication overhead will increase while remapping tasks. Furthermore, technique proposed in [23] assigns tasks dynamically and it is characterized by low utilization. [24] Focuses on integrating task mapping, task ordering and voltage scaling.…”

Section: Related Workmentioning

confidence: 99%

“…In terms of modalities and implementation, majority of the strategies discussed in the related work are identical. For example, the work in [1], [20], [31] [32,33], [34], [24], [28] and [30] are based on the sequential mapping approach. The sequential schemes have high computational complexity and consume significant amount of time and resources, especially when dealing with large workflows, such as brain imaging workflows, health care data analysis, and Pegasus workflow that tackle thousands of tasks [35][36][37].…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

et al. 2021

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Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems. With the increase in computing capabilities of computing hardware, application requirements have increased many folds, particularly for real world scientific applications. Scheduling large scientific workflows consisting hundreds and thousands of tasks consume significant amount of time and resources. In this article, energy aware parallel scheduling techniques are presented primarily aimed at reducing the algorithm execution time while considering network load. Experimental results reveal that the proposed parallel scheduling algorithms achieve significant reduction in execution time.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

et al. 2021

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“…Furthermore, system has natural parallelism and the overall optimization task should be divided into many subtasks to be executed in different membranes [24], [25]. The task allocation method in this paper can be described in the following way.…”

Section: A Optimization Model and Strategy 1) Some Definitionsmentioning

confidence: 99%

Dynamic Placement Optimization for Bio-Inspired Self-Repairing Hardware

Liu

Xiao

et al. 2020

IEEE Access

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Bio-inspired self-repairing hardware is a distributed self-adaptive system, characterized by powerful fault-tolerant ability and environment adaptivity. However, it suffers from some difficulties such as large resource consumption and degraded circuit performances. From the viewpoint of cybernetics and computer science, the cellular differentiation and substitution process of bio-inspired self-repairing hardware can be converted into dynamic placement problems on a reconfigurable system. Current systems can only generate some predefined fault-free placements from a finite number of initial placements. The aim of this paper was to achieve high-quality placements from arbitrary initial placements. Based on P systems, an analysis has been made on the limitations of current systems and an improved computing system has been developed to achieve the ergodic property. Its computational power has been verified by a constructive proof. Moreover, centering on the problem how to improve the placement quality on a distributed platform, the optimization model, task allocation, optimization strategy, and membrane optimization algorithm have been designed and developed. The optimization performances were verified and the calculation amount was exhibited by experiments. Finally, it indicated by comparison that the proposed approach would reduce the resource consumption and maintain good circuit performances. INDEX TERMS Bio-inspired self-repairing hardware, dynamic placement optimization, P systems, computing model, membrane optimization algorithms.

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“…Chip faults exhibit different syndromes and have various causes that affect NoC reliability[18,[25][26][27].…”

mentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

Cited by 31 publications

References 23 publications

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

Dynamic Placement Optimization for Bio-Inspired Self-Repairing Hardware

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

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