TCAD analysis of HCS degradation in LDMOS devices under AC stress conditions

Abstract

Figure 1. Schematic view of the STI-based LDMOS device under investigation. The worst-case HCS degradation in DC stress conditions is obtained at high VDS for VGS = 2 and 6 V, corresponding to the highest electron temperature localized at the STI corner and the highest lattice temperature distribuited along the drift region, respectively [1]. Figure 2. ∆ID,lin vs. stress VGS at high VDS for two different ambient temperatures (TA). Symbols: experiments. Lines: TCAD data.Abstract -Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high VGS biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.