TCAD challenges and opportunities to find a feasible device architecture for sub-3nm scaling

Kwon, Uihui; Park, Yonghee; Kim, Yoon-Suk; Yoo, Jaehyun; Kim, Dae Sin

doi:10.1109/sispad54002.2021.9592554

Cited by 3 publications

(6 citation statements)

References 15 publications

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“…Furthermore, our results match the literature's theoretical and experimental results for the different target applications [5,10,12,14]. Thus, we consider the developed model reliable since it correctly predicts the experimental results in [5,10,12].…”

Section: N-type Ns-gaafetsupporting

confidence: 85%

“…This success allowed FinFET to become the dominant technology until the latest 3-nm node. However, nowadays, Fin-FET technology is facing many challenges in performance, layout, and cost for further scaling, determining its end in the sub-3-nm technological node [5][6][7][8]. Novel TCAD tools, improving the electronics industry toolchain, are currently being developed to investigate cost-effective solutions to still pursue more-than-Moore integration [5].…”

Section: Introductionmentioning

confidence: 99%

“…However, nowadays, Fin-FET technology is facing many challenges in performance, layout, and cost for further scaling, determining its end in the sub-3-nm technological node [5][6][7][8]. Novel TCAD tools, improving the electronics industry toolchain, are currently being developed to investigate cost-effective solutions to still pursue more-than-Moore integration [5]. Nevertheless, power performance appears often as a limiting factor for FinFET-based ICs at ultra-scaled technological nodes, and optimizations in the energy delay product are difficult and still searched for [6].…”

Section: Introductionmentioning

confidence: 99%

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NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Spano

Ardesi

et al. 2023

Electronics

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NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hocresistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

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Section: N-type Ns-gaafetsupporting

confidence: 85%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Spano

Ardesi

et al. 2023

Electronics

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“…In this study, we used the semiconductor simulation software Sentaurus TCAD to design and investigate the performance of β-Ga 2 O 3 MOSFET power devices. By altering the relevant parameters of the device, we obtained the optimal parameters for device performance design [21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2

Zhang,

Luan

2024

Eng. Res. Express

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The Power Figure of Merit (PFOM = Vbr2/Ron,sp) is used to evaluate the performance of Gallium Oxide (β-Ga2O3) power devices. In this study, a lateral β-Ga2O3 MOSFET device is designed. The effects of different gate lengths, gate-drain distances, and epitaxial layer doping concentrations on the device performance are investigated. It is found that when the gate length is 3μm, the breakdown voltage of the device is 3099V, which is approximately twice that of devices with other gate lengths. The PFOM of the device reaches 769.14 MW/cm2. Furthermore, the breakdown voltage exhibits a trend of initially decreasing and then increasing with the increase of the gate-drain distance. When the gate-drain distance is 37μm, the breakdown voltage of the device reaches 4367V. Additionally, it is observed that the device performance is optimal when the epitaxial layer doping concentration is 2×1017cm-3. This study provides a new approach for the design of Gallium Oxide power devices.

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“…Among them, we have chosen an easy-to-fork open-source software called Nebula [4]. We constructed a new framework, implementing Nebula into our TCAD simulation environment to integrate with state-ofthe-art process and device simulators based on multiple advanced physics models needed for SEM simulation [5,6].…”

Section: Introductionmentioning

confidence: 99%

E-beam simulation for advanced SEM applications in semiconductor industry

Cheon,

Moon,

Kwon

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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Scanning Electron Microscopy (SEM) technology makes use of an electron beam (e-beam) with wide energy range from 0.1 to 50 keV, so it is possible to measure wafers from surface to deep and buried structures. Due to its superior accuracy, it is widely used for in-line metrology and inspection (MI) process. As devices scaling down for performance enhancement, the MI process became inaccurate due to the target structure shrinkage and complicated electrons' behavior inside it. To overcome the challenges, accurate simulation tool is required to understand its underlying mechanism theoretically. In this paper, we propose a unifying framework for simulating SEM operation by implementing Nebula e-beam computing algorithm on the Technology Computer-Aided Design (TCAD) environment. The proposed framework integrates various physics models including the scattering and transport behaviors of electrons, which enables to calculate the important trajectories of electrons in the most important regions of wafers. In addition, it gives an expandability on further integration thanks to the computability of TCAD environment. We validate the proposed framework with demonstrating key applications on real products.

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TCAD challenges and opportunities to find a feasible device architecture for sub-3nm scaling

Cited by 3 publications

References 15 publications

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2

E-beam simulation for advanced SEM applications in semiconductor industry

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TCAD challenges and opportunities to find a feasible device architecture for sub-3nm scaling

Cited by 3 publications

References 15 publications

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance

Design of lateral β-Ga2O3 MOSFET with PFOM of 769.42 MW cm–2

E-beam simulation for advanced SEM applications in semiconductor industry

Contact Info

Product

Resources

About

Design of lateral β-Ga₂O₃ MOSFET with PFOM of 769.42 MW cm^–2