TCAD Simulation and Analysis of Drain Current and Threshold Voltage in Single Fin and Multi-Fin FinFET

Chopade, S. S.; Padole, Dinesh

doi:10.17485/ijst/2017/v10i11/93062

Cited by 3 publications

(3 citation statements)

References 17 publications

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“…It is noticed that increasing the W U-fin enhances the I on attributed to the increase in effective width (I d α W eff ). 29 Furthermore, increasing the W U-fin leads to a decrease in source/drain resistance, an increase in carrier density, and a decrease in carrier scattering 40 is also one of the reasons contributing to the increase in I on . The I off also increases with W U-fin due to poor gate control over the channel, resulting in SCEs.…”

Section: Jl-dg-invmentioning

confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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FinFET is considered a potential contender in the era of Multigate field-effect transistors (FETs). Here, we present structural variations for Junctionless FinFET devices at the IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed, JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET. The electrical and analog/RF performance of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/radio frequency characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5×106, 1.2×109, 2.04×108, and 1.1×1010, respectively. Similarly, the SS values are noted as 93.44, 70.87, 70.61, and 62.1 mV/dec for the respective configurations. The effect of variation in geometrical parameters such as gate length, U-shaped fin width, and U-shaped fin height on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET-based common source amplifier produced a gain of 5.2. The results reported will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

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Section: Jl-dg-invmentioning

confidence: 99%

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Ramakrishna,

Valasa,

Bhukya

et al. 2023

ECS J. Solid State Sci. Technol.

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“…DG transistors with fully depleted silicon layer have a distribution of the electrical potential inside the layer, where the potential at the center being different from zero. (Chopade & Padole, 2017b) In this work (Sivasankaran, 2013) researchers focus on comparison of Fin-FET devices with bulk CMOS technology by looking at the characteristics of both devices and their challenges in nano-scale regimes. The channel is surrounded in three dimensions in Fin-FET.…”

Section: Review Of Literaturementioning

confidence: 99%

Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics

Jagtap¹,

Gond

2021

International Journal of Natural Computing Research

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The scrambling of MOSFET below 22nm, 14nm, unwanted Short Channel Effects (SCE) like punch through, drain-induced barrier lowering (DIBL), along with huge leakage current are flowing through the device, which is not recognized for better performance. Multi-gate MOSFET generally measured as Fin-FET is the best substitute vital to stunned short channel effects. The work highlights results of the current-voltage electrical characteristics of the n-channel triple gate Fin-FET gatherings. The paper focuses on the study of geometry-based device design of Fin-FET by changing high k dielectrics materials from silicon SiO2 (3.9), Hafnium Oxide (HfO2), and metal gate work function ranging from 4.1eV to 4.5eV. The approach and simulation of 3Dimensional Fin-FET is carried to evaluate the better performance parameters of device for change in gate length by deploying different dielectrics materials. The effect on ratio of on current (ION) and off current (IOFF), threshold voltage (VTH), subthreshold slope (SS), and drain-induced barrier lowering (DIBL) is observed.

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“…The structure is so-called FinFET because its Si body resembles the back fin of a fish. FinFET [79]- [81] In bulk-MOS (plannar MOS), the channel is horizontal, while in FinFETs channel is vertical. Therefore, in a FinFET, the height of the channel (Fin Height, Hfin) determines the width of the device.…”

Section: Introductionmentioning

confidence: 99%

Silicon- and Graphene-based FETs for THz technology

Notario¹,

Antonio²

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Silicon-and Graphene-based FETs for THz technology This Thesis focuses on the study of the response to Terahertz (THz) electromagnetic radiation of different silicon substrate-compatible FETs. Strained-Si MODFETs, state-ofthe-art FinFETs and graphene-FETs were studied. The first part of this thesis is devoted to present the results of an experimental and theoretical study of strained-Si MODFETs. These transistors are built by epitaxy of relaxed-SiGe on a conventional Si wafer to permit the fabrication of a strained-Si electron channel to obtain a high-mobility electron gas. Room temperature detection under excitation of 0.15 and 0.3 THz as well as sensitivity to the polarization of incoming radiations were demonstrated. A two-dimensional hydrodynamic-model was developed to conduct TCAD simulations to understand and predict the response of the transistors. Both experimental data and TCAD results were in good agreement demonstrating both the potential of TCAD as a tool for the design of future new THz devices and the excellent performance of strained-Si MODFETs as THz detectors (75 V/W and 0.06 nW/Hz 0.5). The second part of the Thesis reports on an experimental study on the THz behavior of modern silicon FinFETs at room temperature. Silicon FinFETs were characterized in the frequency range 0.14-0.44 THz. The results obtained in this study show the potential of these devices as THz detectors in terms of their excellent Responsivity and NEP figures (0.66 kV/W and 0.05 nW/Hz 0.5). Finally, a large part of the Thesis is devoted to the fabrication and characterization of Graphene-based FETs. A novel transfer technique and an in-house-developed setup were implemented in the Nanotechnology Clean Room of the USAL and described in detail in this Thesis. The newly developed transfer technique enables to encapsulate a graphene layer between two flakes of h-BN. Raman measurements confirmed the quality of the fabricated graphene heterostructures and, thus, the excellent properties of encapsulated graphene. The asymmetric dual grating gate graphene FET (ADGG-GFET) concept was introduced as an efficient way to improve the graphene response to THz radiation. High quality ADGG-GFETs were fabricated and characterized under THz radiation. DC measurements confirmed the high quality of graphene heterostructures as it was shown on Raman measurements. A clear THz detection was found for both 0.15 THz and 0.3 THz at 4K when the device was voltage biased either using the back or the top gate of the G-FET. Room temperature THz detection was demonstrated at 0.3 THz using the ADGG-GFET. The device shows a Responsivity and NEP around 2.2 mA/W and 0.04 nW/Hz 0.5 respectively at respectively at 4K. It was demonstrated the practical use of the studied devices for inspection of hidden objects by using the in-house developed THz imaging system.

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TCAD Simulation and Analysis of Drain Current and Threshold Voltage in Single Fin and Multi-Fin FinFET

Cited by 3 publications

References 17 publications

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics

Silicon- and Graphene-based FETs for THz technology

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