Technical Study on Low Power VLSI methods

Kapilachander, T.; Shanavas, I. Hameem; Venkataraman, Vyas

doi:10.5815/ijieeb.2012.01.08

Cited by 2 publications

(3 citation statements)

References 21 publications

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“…The multiplexer is a combinational logic circuit that selects an appropriate analogue (or) digital signal from several input signals and forwards it to a single output line. 11 A multiplexer has several input lines and a single output line. The selection of the appropriate input is based on unique control lines called select lines.…”

Section: Methodsmentioning

confidence: 99%

“…(1) The equation (1) was expanded using associative and commutative laws to obtain an appropriate and optimized circuit equation for implementing the multiplexer. 11 Any single input line is selected instantly depending on the combination of select lines input to be connected to the output Z. For example, if the select lines combination S 1 S 0 is a logic '0' a logic '1' (01), then input line I 1 would be connected to the output Z, referring to Table 1.…”

Section: Multiplexer (Mux)mentioning

confidence: 99%

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Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

2022

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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Section: Methodsmentioning

confidence: 99%

Section: Multiplexer (Mux)mentioning

confidence: 99%

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

2022

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show abstract

“…The equation (1) was expanded using associative and commutative laws to obtain an appropriate and optimized circuit equation for implementing the multiplexer. 11 Any single input line is selected instantly depending on the combination of select lines input to be connected to the output Z. Adding more control address lines (n) allowed the multiplexer to control more inputs to switch 2 n inputs.…”

Section: Multiplexer (Mux)mentioning

confidence: 99%