No abstract

In Digital Image Processing, Median Filter is used to reduce the noise in an image. The med ian filter considers each pixel in the image and replaces the noisy pixel by the median of the neighbourhood pixels. The median value is calculated by sorting the p ixels. Sorting in turn consists of comparator which includes adders and mult iplier. Multip lication is a fundamental operation in arith metic co mputing systems and is used in many DSP applications such as FIR Filters. The adder circuit is used as a main component in the mu ltip lier circuits. The Carry Save Array (CSA) mu ltip lier is designed by using the proposed adder cell based on mult iplexing logic. The proposed adder circu it is designed by using Shannon theorem.The mu ltiplier circuits are schematised and their layouts are generated by using VLSI CAD tools. The proposed adder based mu ltip lier circuits are simulated and results are compared with CPL and other circuit designed using Shannon based adder cell in terms of power and area and the intermediate state involved in the circuit is eliminated.The proposed adder based mu ltiplier circu its are simulated by using 90n m feature size and with various supply voltages. The Shannon full adder circu it based mu ltip lier circu its gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder circuit.

Abstract-In recent days every application must need power management and area management such physical problems and aspects of VLSI design. Minimization of power and area are highly complex integrated systems in microelectronics have led to the 3 Dimension developments a technological approach. 3 Dimension offers numerous advantages: Size, power consumption, hybrid integration etc., various techniques to handle the power management in IC. Power dissipation in a IC is base on power used by the IC and also by heat dissipation. To reduce energy use or to minimize heat dissipation some of the techniques are available. Three-dimensional (3D) integration is a viable approach that allows designers to add functionality to the devices while maintaining the same die area without the need for new design process. Stack dies in 3D integrated circuits (ICs) also reduces the die area of designs. In addition, die area reduction helps decrease wire length, thus improving the performance of the designs.