Techniques for high-speed implementation of nonlinear cancellation

Kasturia, S.; Winters, J.H.

doi:10.1109/49.87640

Cited by 134 publications

(60 citation statements)

References 8 publications

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“…Extra combinational logic can be employed to extend the loop delay by one clock cycle and overcome the speed bottleneck [25], as shown in Fig. 12(b).…”

Section: Digital Equalizermentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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“…Extra combinational logic can be employed to extend the loop delay by one clock cycle and overcome the speed bottleneck [25], as shown in Fig. 12(b).…”

Section: Digital Equalizermentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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“…High speed binary receivers with DFE usually implement a loop-unrolling technique to overcome the critical 1 unit interval (UI) feedback path [10]. The straight forward implementation of a flash ADC with embedded 1-tap loop-unrolled DFE is shown in Fig.…”

Section: B Embedded Dfementioning

confidence: 99%

Embedded equalization for ADC-based serial I/O receivers

Shafik

Lee

Tabasy

et al. 2011

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

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“…For higher speed applications, the second approach is proposed to reformulate the FBF as two-stage pre-computation. For M-PAM modulations and a L-tap FBF with wordlength W, we can reduce the hardware overhead to about 2(log 2 M) (-L/2) times of [1] [2]. The iteration bound is only 2(log 2 W+2)/L+(log 2 M) multiplexer-delays.…”

Section: Introductionmentioning

confidence: 96%

“…The delay time of one multiplexer is 0.14 ns in UMC 0.18 m process technique. Again, the computation speed of the architecture [1] [2] can not provide a delay element with enough margins. Despite that unfolding approach can be employed to achieve the desired throughput rate, the overhead will be extremely large.…”

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confidence: 99%

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Low Cost Decision Feedback Equalizer (DFE) Design for Giga-Bit Systems

Lin¹,

Wu²

Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

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ABSTRACT. The required hardware overhead should be more severe when the DFE is designed in parallel. In this paper, we propose two new approaches to implement the DFE when Giga-bit speed is required. The first approach is partial pre-computation, which can trade-off between hardware complexity and computation speed. The second approach is two-stage pre-computation, which can be applied to higher speed applications. We can reduce the hardware overhead to about 2(log 2 M) (-L/2) [5]. Another approach to achieve high speed computation is parallel implementation [6] [7]. We can relax the clock time to N-times for N-parallel implementation. Exploiting both pipeline and parallel processing for high speed applications are straightforward for non-recursive computations. However, recursive computations, such as DFEs, can not be easily pipelined or processed in parallel due to the feedback loops in these filters. For a filter with a loop, retime approach [9] can be used to move the delay elements of a shorter path to a longer path in loops; then, a smaller critical path can be obtained. However, retime approach can not shorten the iteration bound. Moreover, retime approach can not achieve the iteration bound in most cases. In order to achieve iteration bound, we can unroll a loop, which is referred as the unfolding scheme [5] [7], and then apply the retiming approach.However, for gigabits throughput rate in each communication path, all the aforementioned approaches can not achieve the desired speed. Fig. 1 is a conventional DFE architecture. The critical path of this DFE is one multiplier, one slicer, and two adders as drawn in bold line. For Ethernet 10G base LX4 [11], the modulation scheme is 2-PAM; therefore, the multiplier can be replaced by one 2-to-1 multiplexer. The iteration bound reduces to one multiplexer and two adders. This critical path does not meet the required speed, i.e., 0.32 ns. The authors of [1][2] reformulate the FBF as 2 L -to-1 multiplexers. The iteration bound is reduced to one multiplexer. The delay time of one multiplexer is 0.14 ns in UMC 0.18 m process technique. Again, the computation speed of the architecture [1][2] can not provide a delay element with enough margins. Despite that unfolding approach can be employed to achieve the desired throughput rate, the overhead will be extremely large.In this paper, both hardware cost and computation speed are taken into account. Motivated by [1][2], two new approaches are proposed in this paper. The first approach is to pre-compute and sum the partial outputs of the FBF. This approach can be used to trade off between hardware complexity and computation speed. For higher speed applications, the second approach is proposed to reformulate the FBF as two-stage pre-computation. For M-PAM modulations and a L-tap FBF with wordlength W, we can reduce the hardware overhead to about 2(log 2 M) (-L/2) times of [1] [2]. The iteration bound is only 2(log 2 W+2)/L+(log 2 M) multiplexer-delays. Fig. 1 The architecture of a DFE and its iteration bound. REVIEW OF T...

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Techniques for high-speed implementation of nonlinear cancellation

Cited by 134 publications

References 8 publications

ADC-Based Backplane Receivers: Motivations, Issues and Future

ADC-Based Backplane Receivers: Motivations, Issues and Future

Embedded equalization for ADC-based serial I/O receivers

Low Cost Decision Feedback Equalizer (DFE) Design for Giga-Bit Systems

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