Techniques for modulating error resilience in emerging multi-value technologies

Abstract

There exist extensive ongoing research e↵orts on emerging atomic scale technologies that have the potential to become an alternative to today's CMOS technologies. A common feature among the investigated technologies is that of multivalue devices, in particular, the possibility of implementing quaternary logic and memory. However, multi-value devices tend to be more sensitive to interferences and, thus, have reduced error resilience. We present an architecture based on multi-value devices where we can trade energy e ciency against error resilience. Important data are encoded in a more robust binary format while error tolerant data is encoded in a quaternary format. We show for eight benchmarks an average energy reduction of 14%, 20%, and 32% for the register file, level-one data cache, and main memory, respectively, and for three integer benchmarks, an energy reduction for arithmetic operations of up to 28%. We also show that for a quaternary technology to be viable a raw bit error rate of one error in 100 million or better is required.

Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training

“…To mitigate the demerits of multi-valued computation, some algorithmic techniques, such as Error Correction Coding (ECC) can be considered in memristor-crossbar-based networks. Actually, ECC has been common in modern state-of-the-art memory technologies, such as DRAM, FLASH, etc., regardless of the binary and multi-valued circuits, for many years [41].…”

Evaluating the Potential Applications of Quaternary Logic for Approximate Computing

“…These designs are based on basic quaternary logic gates that can also produce binary results (Fig. 2), as discussed by Själander et al [44]. We also propose memories able of storing both binary and quaternary data, although not in as much detail, since memories with multi-level cells are already common in storage solutions such as SSDs.…”

“…Kogge-Stone adder is described in our previous work [44], so here we will only provide an overview. When the adder is operated in quaternary mode, only the right half (separated by the gray dotted line in the figure) is fed with data.…”

“…In our previous work [44,45], we have proposed a cache design that can store both binary and quaternary data (Fig. 6), without the need to have a statically defined split between binary and quaternary cache lines.…”