Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs

Abstract

Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently.

Design and Analysis of Low Power Level Shifter in IC Applications

“…In the exterior path, the design mostly includes a charge pump circuitry that introduces a reverse body bias voltage and a voltage divider to introduce a forward body bias voltage. Reverse body bias method employ a negative body-to-source voltage to NMOS transistor and thus rises the threshold voltage [9]. Though, a positive body-tosource voltage is applied to NMOS transistor in Forward body biasing, this reduces the threshold voltage.…”

“…Where, dynamic body biasing reduces temperature and age effect. This adjusts power management modes too effective at optimizing very low power operation [9]. So, leakage current minimization can be achieved by using RBB thereby reducing the threshold voltage of transistors in the standby nature.…”