Technology migration technique for designs with strong RET-driven layout restrictions

Abstract

Restrictive design rules (RDRs) have been introduced as a simplified layout optimization method to better enable resolution enhancement techniques in ultra-deep submicron designs [16]. In this paper, we study the technology migration problem for designs with strong RET-driven layout restrictions, i.e., RDR constraints, which require devices (gates) to be placed on a coarse pitch and in a single orientation. In particular, we study the legalization problem with on-pitch constraints for devices with an objective of minimum layout perturbation. The problem can be formulated as an integer linear programming (ILP) problem with a set of stringent integer constraints, and it can be approximated as a mixed integer linear programming (MILP) problem. Instead of using an MILP solver to solve it, we propose a two-stage method -first the target on-pitch positions for gates are computed and second the original problem is relaxed to a linear programming problem. Library cell layouts designed in a technology with conventional ground rules have been migrated successfully to a technology with RDRs using our approach.

Layout Decomposition and Legalization for Double-Patterning Technology

“…19(c). In this case, the restrictive DR of poly on grid are met by modifying the LP program as described in [20]. A summary of the results is given in 9 Because DP was assumed for M1 in the process and to avoid making inadequate assumptions on the differences between the spacing values that we cannot justify, we use the same value for the different rules in the experiments.…”

“…According to the total unimodularity property [19], when all X init i and d ij are integers, the solution of the problem consists of integers only. The handling of gridded design rule constraints can be achieved as in [20]. The target on-grid locations are determined and on-grid constraints are relaxed to spacing constraints between the target locations and the cell boundary.…”

“…The target on-grid locations are determined and on-grid constraints are relaxed to spacing constraints between the target locations and the cell boundary. After this relaxation, the problem is still formulated and solved as an LP as detailed in [20].…”

Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization

“…As ongoing works, we are developing an extension of the timing model to apply the proposed method to multistage transistor networks and taking other manufacturability metrics, such as layout regularity [5], into consideration.…”

Technology migration techniques for simplified layouts with restrictive design rules

“…Later, Zhu et al [16] presented an integer linear programming (ILP)-based approach to preserve the geometric closeness in the layout migration, in the similar manner of minimum layout perturbation. Most recently, Yuan et al [15] addressed the problem of putting polysilicon conductors on grid during the technology migration process. However, none of these works addresses the problems of abstracting layout shapes into simple geometric objects and legalizing them to satisfy the multiple grid constraints.…”