Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

Abstract

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 mV/℃, and its static current consumption is found to be only 0.83 μA@2.0 V. Keywords: Pseudo SRAM, memories, RCAT, temperature, back-bias voltage generator. Manuscript received June 23, 2009; revised Oct. 28, 2009; accepted Nov. 12, 2009. This work was supported by the Korea Foundation for International Cooperation of Science & Technology (KICOS) through a grant provided by the Korea Ministry of Science & Technology (MOST) (K20601000002-07E0100-00220) and of Seoul Program (10920) and was developed within the scope of Human Resource Development Project for IT SoC Architect.Jong-Pil Son (phone: +82 31 208 0695, email: jp.son@samsung.com), Young-Hyun Jun (email: yhjun.jun@samsung.com), and Kinam Kim (email: kn_kim@samsung.com) are with the Memory Division, Samsung Electronics Corporation, Hwasung, Rep. of Korea.Hyun-Geun Byun (email: hgbyun@samsung.com) is with the Department of Semiconductor, SSIT, Samsung Electronics Corporation, Yongin, Rep. of Korea.Soo-Won Kim (email: ksw@korea.ac.kr) is with the Department of Electronics Engineering, Korea University, Seoul, Rep. of Korea. doi:10.4218/etrij.10.0109.0366 I. IntroductionRecently, the density of memories for mobile applications has continuously increased with the downward scaling of process technology, but there is still a need for less power consumption and simultaneously, higher operating speed. Further scaling of the process causes short channel effects in the cell transistors and increases their leakage currents. This increased leakage makes the data retention time shorter and makes the memory consume more power. The pseudo SRAM is a memory for mobile applications using the SRAM interface with the 1T or 2T cell array of DRAM instead of the 6T SRAM cell array. Using a DRAM cell array makes the die size small and reduces the cost. However, it also requires hidden refresh operations and lower standby current because it uses the SRAM interface. The recessed channel array transistor (RCAT) pseudo SRAM that has been generally used in recent years has the advantages of lower leakage and scalability compared to the planar transistor RAM [1]- [3]. Even though the RCAT process reduces the leakage drastically, it still has several kinds of leakage that should be considered to determine the data retention time. Using the RCAT process, the cell drivability (cell saturation current) should also be considered because t...

Analysis of read speed latency in 6T‐SRAM cell using multi‐layered graphene nanoribbon and cu based nano‐interconnects for high performance memory circuit design

“…Nonvolatile SRAM is a type of memory that can store information or digital bits even when the power supply is off. Nonvolatile SRAM consists of a single 6T‐SRAM cell and double floating gate transistors [20, 21]. According to reports, almost 90%–95% of integrated circuits (ICs) generate 51% of the delay due to incorrect modeling of the interconnect and 49% of the delay due to gate or device delay [22, 23].…”