Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability

Sharma, Suruchi; Basu, Rikmantra; Kaur, Baljit

doi:10.1109/ted.2022.3156895

Cited by 18 publications

(10 citation statements)

References 29 publications

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“…in the sub-threshold region of I D − V G characteristics, illustrative of an exponential relationship with temp. [36,37] as expressed in equation (3).…”

Section: Results and Performance Analysismentioning

confidence: 99%

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Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Dewan,

Chaudhary,

Singh

et al. 2024

Eng. Res. Express

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The Doping Less Tunnel Field Effect Transistor (DL-TFET) is gaining recognition as a promising TFET structure due to its resistance to random dopant fluctuations (RDFs) and the elimination of high thermal budgets and costly annealing techniques. However, temperature sensitivity remains a critical factor in assessing the device’s reliability, as the bandgap of the semiconductor material (Eg) varies with temperature fluctuations. Therefore, this study investigates the impact of temperature changes (ranging from 240 to 360 Kelvin) on thelinearity and RF/analog characteristics of a Heterojunction (HJ), Double Gate (DG), Doping Less (DL) TFET.The analysis encompasses various RF/analog and DC parameters, including ID − VG characteristics, ID − VD characteristics, gm (transconductance), gd (output conductance), fT (cut-off frequency), GBP (Gain Bandwidth Product), TGF (transconductance generation factor), and TFP (transconductance frequency product). These parameters are evaluated using the ATLAS simulation tool, taking into account the influence of temperature fluctuations. Furthermore, the study considers temperature variations when assessing linearity characteristics such as the second-order Voltage Intercept Point (VIP2), third-order Voltage Intercept Point (VIP3), intermodulation distortion (IMD3), and third-order input interception point (IIP3).

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“…in the sub-threshold region of I D − V G characteristics, illustrative of an exponential relationship with temp. [36,37] as expressed in equation (3).…”

Section: Results and Performance Analysismentioning

confidence: 99%

“…Temperature dependence of dc/static characteristics Here, the impact of temp. change (from 240 K to 360 K) in the gap of 30 K on the proposed HJ-DG-DLTFETs DC performance characteristics, such as I ON , I OFF , I ON /I OFF ratio, SS, and V TH is investigated[38,39]. The effect of temp.…”

mentioning

confidence: 99%

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Dewan,

Chaudhary,

Singh

et al. 2024

Eng. Res. Express

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“…Higher peak of VIP2 and VIP3 indicates that with lower temperature indicates improved linearity behaviour at temperature of 200 K than 500 K. Therefore, Graphene based GO-SSDG-TFET is an emerging device in future for semiconductor industry due to improved behaviour in presence of ITCs and temperature. 67.5 HS-TFET 23 2.12 × 10 −8 8.96 × 10 −18 2.37 × 10 9 10 −6 0.04 Heterojunction DG-TFET 21 6.64 × 10 −4 10 −14 6.64 × 10 10 920 14.86 DMGOS DG-TFET 35 2.1 × 10 −5 10 −15 2.1 × 10 10 81.34 9.23 Dopingless -TFET 24 2 × 10 −5 4 × 10 −14 5 × 10 8 150 24.2 GO-Ge-SSDG TFET 26 6.2 × 10…”

Section: Discussionmentioning

confidence: 99%

“…23 The high frequency and linearity performance are extracted for SiGe-GaAs charge plasma junctionless TFETs. 24 The incorporation of a dielectric pocket section near the drain lowers the ambipolar current in nanotubes. 25 ITCs for positive and negative polarity affect RF/analog and linearity parameters GO-G-SSDG-TFET.…”

mentioning

confidence: 99%

Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Saha¹,

Goswami²,

Hoque³

2023

ECS J. Solid State Sci. Technol.

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This work evaluates the electrical parameters of Gate Overlap Graphene source Step Shape Double Gate TFET (GO-GR-SSDG-TFET) with wide variation in interface trap charges (ITCs) and temperature. Here, both the positive interface charges (PITCs) and negative interface charges (NITCs) along with temperature ranges from 200-500 K on DC, RF/analog and linearity characteristics are analyzed using TCAD Sentaurus Simulator. It is observed that there is improvement (degradation) in current ratio, transconductance, gain, cut-off frequency, and delay with increase (decrease) in PITC (NITC), whereas, opposite trend is realized in terms of linearity parameters. The rise in temperature leads to degradation is subthreshold behaviour due to exponential characteristic of Shockley-Read-Hall (SRH) recombination with temperature. It is also seen that at high temperature there is degradation transconductance, device efficiency, cut-off frequency, current ratio, delay, and temperature sensitivity (ST) in the proposed TFET. Moreover, the linearity parameters are degraded with rise in temperature. Finally, a comparison table is highlighted in terms of various electrical parameters for proposed TFET with existing data.

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“…Most of the trap charges may have been inactive at lower temperatures. Thus, the ITCs are temperature-dependent [40]. Hence, the temperature-dependent DC, Analog/RF, and Linearity characteristics of the Ge CP-DGTFET device structure under the influence of the ITC are imperative for low-power switching and analog device applications.…”

Section: Introductionmentioning

confidence: 99%

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

Yadav,

Chappa,

Baghel

et al. 2024

Eng. Res. Express

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The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (ION), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor (CP-DGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional ION, ION/IOFF ratio, and minimal sub-threshold swing (S) of ~3.04×10-4 A/µm, ~1.2×1010, and ~3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of ~0.75 mS/µm, ~0.97 THz, and ~0.10 THz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature-dependent analysis showed that the OFF-state leakage current increases from ~1.7×10-15 A/µm to 2.4×10-10 A/µm with temperature fluctuations from 275 K to 375 K. Overall, the work function-engineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology.

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Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability

Cited by 18 publications

References 29 publications

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET

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Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability

Cited by 18 publications

References 29 publications

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

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Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO₂/Al₂O₃/Ge, double gate TFET