Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Abstract

Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultralow-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced technology nodes. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to efficiently compensate, at run-time, these variations. The proposed method exploits on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with on-chip low-power Body Bias Generators. We characterize the response of the PMBs versus the maximum achievable frequency of the system, deriving a predictive model able to estimate such frequency with an error of 3%. We apply this model to compensate Temperature-induced performance variations, estimating the maximum frequency with an error of 7%; we eliminate the error by adding an appropriate body-bias margin resulting in a worst case global power consumption overhead of 5%. As further improvement, we generalize the methodology to compensate also process variations, obtaining an error of 28% on the estimated maximum performance and compensating this error with an overhead of 17% on the global power consumption.

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

“…Every power domain features a Process Monitoring Box (PMB) capable to probe the maximum achievable switching frequency of both P and N ring oscillators. The maximum frequency value returned by these modules, as demonstrated in [6], changes consistently with the maximum frequency of the entire power domain where they are placed, thus they can be used as on-chip frequency-meters.…”

Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors

“…In Fig. 13, which compares the ION/IOFF ratio obtained for both structures taking the condition where the standard-nMOS devices present the higher ratio (Ptype GP), the ULP structure shows a ratio of 2×10 10 down to 1×10 8 and 2×10 6 down to 3×10 5 for the 100 and 25 nm long devices at VSUB = -2 V and |VD| of 1 and 0.5 V respectively, while the standard-nMOS presents 3×10 8 down to 8×10 6 for the 100 nm long device and the shorter one exhibits 2×10 4 for both |VD| at the same analysis. 2 presents the threshold voltage as a function of the substrate bias for both ULP and standard diodes with and without ground planes.…”

“…These UTBB features are responsible for making the device suitable for low power analog [2] and RF [3] applications, and also in Ultra-Low-Power (ULP) systems [4][5][6], where low threshold voltage and low leakage current are required. One of these applications consists in RF diodes, frequently used in energy harvesting systems [7][8][9].…”

Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor

“…Despite technological scaling, which reduces the margins for supply voltage regulation, DVFS still represents a viable energy saving techniques for modern platforms operating near threshold [4]. Those platforms reach high energy efficiencies thanks to a combination of voltage scaling and adaptive body biasing to avoid performance degradation [5,6]. In [7,8], authors present two approaches where DVFS is controlled by dedicated hardware units on embedded microprocessors.…”